mr2a08am Everspin Technologies, Inc, mr2a08am Datasheet - Page 9

• Manufacturer Part Number: mr2a08am
• Description: 512k X 8 Mram Memory
• Manufacturer: Everspin Technologies, Inc

Everspin Technologies © 2011
Timing Specifications
1
2
3
All write cycle timings are referenced from the last valid address to the first transition address.
Parameter
Write cycle time
Address set-up time
Address valid to end of write (
Address valid to end of write (
Write pulse width (
Write pulse width (
Data valid to end of write
Data hold time
Write low to data Hi-Z
Write high to output active
Write recovery time
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given
voltage or temperate, t
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
A (ADDRESS)
D (DATA IN)
2
G
G
high)
low)
3
WLQZ
(max) < t
3
G
G
Figure 3.4 Write Cycle Timing 1 (W Controlled)
Table 3.4 Write Cycle Timing 1 (W Controlled)
high)
low)
Hi -Z
WHQX
(min)
t
AVWL
t
t
WLQZ
AVWH
9
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVAV
AVWL
AVWH
AVWH
WLWH
WLEH
WLWH
WLEH
DVWH
WHDX
WLQZ
WHQX
WHAX
AVAV
t
t
WLEH
WLWH
Document Number: MR2A08AM Rev. 0, 2/2011
Hi -Z
Min
35
0
18
20
15
15
10
0
0
3
12
t
DVWH
DATA VALID
1
Max
-
-
-
-
-
-
-
-
12
-
-
MR2A08AM
t
t
WHDX
WHAX
t
WHQX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns