si5325 Silicon Laboratories, si5325 Datasheet - Page 3

• Manufacturer Part Number: si5325
• Description: ?p-programmable Precision Clock Multiplier
• Manufacturer: Silicon Laboratories

Table 1. Performance Specifications (Continued)
(V
Table 2. Absolute Maximum Ratings
PLL Performance
Jitter Generation
Jitter Transfer
Phase Noise
Subharmonic Noise
Spurious Noise
Package
Thermal Resistance
Junction to Ambient
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
DC Supply Voltage
LVCMOS Input Voltage
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pF, 1.5 kΩ); All pins except
CKIN+/CKIN–
ESD MM Tolerance; All pins except CKIN+/CKIN–
ESD HBM Tolerance (100 pF, 1.5 kΩ); CKIN+/CKIN–
ESD MM Tolerance; CKIN+/CKIN–
Latch-Up Tolerance
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
DD
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
Clock Family Reference Manual. This document can be downloaded from
Documentation)
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Parameter
.
Parameter
Symbol
SP
SP
CKO
J
J
θ
GEN
SUBH
SPUR
PK
JA
PN
A
= –40 to 85 ºC)
(n > 1, n x F3 < 100 MHz)
f
Phase Noise @ 100 kHz
f
IN
IN
LVPECL output format
Max spur @ n x F3
= f
= f
Preliminary Rev. 0.3
50 kHz–80 MHz
12 kHz–20 MHz
Test Condition
100 kHz offset
OUT
100 Hz offset
OUT
10 kHz offset
1 MHz offset
1 kHz offset
Still Air
Offset
= 622.08 MHz,
= 622.08 MHz
Symbol
T
V
T
V
STG
JCT
DIG
DD
www.silabs.com/timing
Min
—
—
—
—
—
—
—
—
—
—
—
–0.3 to (V
–0.5 to 3.6
–55 to 150
–55 to 150
JESD78 Compliant
Value
TBD
TBD
TBD
TBD
TBD
0.05
TBD
TBD
200
700
150
Typ
0.6
0.6
38
2
DD
+ 0.3)
(click on
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.1
Si5325
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps rms
ps rms
Unit
ºC/W
kV
Unit
C
C
dBc
dBc
V
V
V
V
V
dB
3