isl12057 Intersil Corporation, isl12057 Datasheet - Page 11

• Manufacturer Part Number: isl12057
• Description: Low Cost And Low Power I 2c Rtc Real Time Clock/calendar
• Manufacturer: Intersil Corporation

Note: X is don’t care, it can be set to 0 or 1.
Following is example of Alarm1 Interrupt.
Example – A single alarm will occur on Monday at 11:30am
(Monday is when DW = 2).
A. Set Alarm1 registers as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the A1F bit in the
status register to “1”.
Alarm2 Registers
Addresses [Address 12h to 14h]
The Alarm2 register bytes are set up identical to the RTC
register bytes except that the MSB of each byte functions as
an enable bit (enable = “0”). These enable bits specify which
alarm registers (minutes, hour, and date/day) are used to
A1DW/DT A1M1 A1M2 A1M3 A1M4
REGISTER
A1DW/DT
ALARM1
TABLE 6. ALARM1 INTERRUPT WITH ENABLE BITS
A1MN
A1HR
A1SC
X
0
1
0
0
0
0
0
1
1
.
.
.
.
7 6 5 4 3 2 1 0 HEX
1 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 1
0 1 0 0 0 0 1 0
SELECTION (Continued)
1
1
1
0
0
0
1
0
1
0
.
.
.
.
1
1
1
0
1
0
0
0
0
0
.
.
.
.
BIT
0
1
1
1
0
0
0
0
0
0
.
.
.
.
11
1
0
0
1
1
0
0
0
0
0
.
.
.
.
Match Second and Minute
Match Minute, Hour, and
80h Seconds disabled
30h Minutes set to 30,
51h Hours set to 11am,
42h Day set to 1,
Match Second and Hour
Match Minute Hour and
ALARM1 INTERRUPT
Match Second, Minute,
Match Second, Minute
Match Second, Minute
Hour and Date
Hour, and Day
enabled
enabled
enabled
Match Hour
Match Date
Match Day
and Hour
DESCRIPTION
Date
Day
.
.
.
.
ISL12057
make the comparison. When all the enable bits are set to “1”,
the Alarm2 will trigger once per minute. Note that there are
no alarm bytes for second, month and year.
The Alarm2 function works as a comparison between the
Alarm2 registers and the RTC registers. As the RTC
advances, the Alarm2 will be triggered once a match occurs
between the Alarm2 registers and the RTC registers. Any
one Alarm2 register, multiple registers, or all registers can be
enabled for a match.
To clear an Alarm2, the A2F status bit must be set to “0” with
a write.
Note: X is don’t care, it can be set to 0 or 1.
Following is example of Alarm2 Interrupt.
Example – A single alarm will occur on every 1st day of the
month at 20:00 military time.
A. Set Alarm registers as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 20:00 on Monday (after minutes
changes from 59 to 00) by setting the A2F bit in the status
register to “1”.
A2DW/DT A2M2
REGISTER
A2DW/DT
ALARM2
A2MN
A2HR
X
X
X
X
0
1
0
0
0
1
1
1
TABLE 7. ALARM2 INTERRUPT WITH ENABLE BITS
7 6 5 4 3 2 1 0 HEX
1 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0
0 0 0 0 0 0 0 1
1
0
1
1
1
0
1
0
0
0
1
0
A2M3
1
1
0
1
1
0
0
1
0
1
0
0
SELECTION
BIT
A2M4
1
1
1
0
0
1
0
0
0
0
0
0
Match Minute, Hour, and Date
Match Minute, Hour, and Day
Every Minute (Second=00)
Match Minute and Hour
Match Minute and Date
ALARM2 INTERRUPT
Match Minute and Day
Match Hour and Date
Match Hour and Day
80h Minutes disabled
20h Hours set to 20,
01h Date set to 1st,
Match Minute
Match Hour
Match Date
Match Day
enabled
enabled
DESCRIPTION
June 15, 2009
FN6755.0