isl12057 Intersil Corporation, isl12057 Datasheet - Page 12

• Manufacturer Part Number: isl12057
• Description: Low Cost And Low Power I 2c Rtc Real Time Clock/calendar
• Manufacturer: Intersil Corporation

I
The ISL12057 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12057 operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 7). On power-up of the ISL12057, the SDA pin is in
the input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL12057 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
2
C Serial Interface
2
C interface operations must begin with a START
SDA OUTPUT FROM
SDA OUTPUT FROM
TRANSMITTER
SCL FROM
RECEIVER
SDA
SCL
MASTER
2
12
C interface is conducted by
START
FIGURE 7. VALID DATA CHANGES, START, AND STOP CONDITIONS
START
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
HIGH IMPEDANCE
1
STABLE
DATA
ISL12057
CHANGE
DATA
Figure 7). A START condition is ignored during the power-up
sequence.
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 7). A STOP condition at the end of
a read operation or at the end of a write operation to memory
only places the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting 8 bits. During the ninth clock cycle, the receiver
pulls the SDA line LOW to acknowledge the reception of the
8 bits of data (see Figure 8).
The ISL12057 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL12057 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
2
C interface operations must be terminated by a STOP
STABLE
DATA
8
HIGH IMPEDANCE
STOP
ACK
9
June 15, 2009
FN6755.0