isl62881 Intersil Corporation, isl62881 Datasheet - Page 18

• Manufacturer Part Number: isl62881
• Description: Single-phase Pwm Regulator For Imvp-6.5? Mobile Cpus And Gpus
• Manufacturer: Intersil Corporation

domain relationship between inductor total current I
and C
Transfer function A
inductor DCR value increases as the winding temperature
increases, giving higher reading of the inductor DC
current. The NTC R
temperature decreases. Proper selections of R
R
inductor total DC current over the temperature range of
interest.
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the
NTC network and the R
divider, V
voltage. It is recommended to have a higher ratio of V
to the inductor DCR voltage, so the droop circuit has
higher signal level to work with.
A typical set of parameters that provide good
temperature compensation are: R
R
(ERT-J1VR103J). The NTC network parameters may need
to be fine tuned on actual boards. One can apply full load
DC current and record the output voltage reading
immediately; then record the output voltage reading
again when the board has reached the thermal steady
state. A good NTC network can limit the output voltage
drift to within 2mV. It is recommended to follow the
Intersil evaluation board layout and current-sensing
network parameters to minimize engineering time.
V
controller to achieve good transient response. Transfer
function A
to match ω
frequencies. By forcing ω
the solution, Equation 12 gives C
R
A
ω
ω
V
p
p
Cn
cs
ntcnet
sns
Cn
L
= 11kΩ, R
and R
(s) also needs to represent real-time I
s ( )
=
s ( )
n
=
DCR
-------------
=
voltage V
L
------------------------------------------------------- -
R
----------------------------------------- -
R
=
=
ntc
---------------------- -
1
ntcnet
ntcnet
cn
⎛
⎜
⎝
(
----------------------------------------------------
1
cs
+
----------------------------------------- -
R
R
R
L
+
is always a fraction of the inductor DCR
(s) has a pole ω
ntcs
ntcs
ntcnet
------------ -
ω
parameters ensure that V
and ω
------ -
ω
ntcs
sns
s
s
R
L
×
+
ntcnet
+
+
1
R
R
Cn
R
R
sum
sum
= 2.61kΩ and R
+
sns
ntc
ntc
cs
R
ntc
(s):
sum
(s) always has unity gain at DC. The
)
×
+
so A
×
values decreases as its
C
R
sum
R
n
×
p
L
p
DCR
18
cs
equal to ω
sns
resistors form a voltage
(s) is unity gain at all
⎞
⎟
⎠
and a zero ω
×
I
n
o
ntc
sum
s ( )
value.
sns
= 10kΩ
×
Cn
= 3.65kΩ,
A
cs
and solving for
represents the
s ( )
o
ISL62881, ISL62881B
(s) for the
L
. One needs
sum
, R
(EQ. 10)
(EQ. 11)
(EQ. 7)
(EQ. 8)
(EQ. 9)
ntcs
o
(s)
cn
,
FIGURE 14. DESIRED LOAD TRANSIENT RESPONSE
FIGURE 15. LOAD TRANSIENT RESPONSE WHEN C
FIGURE 16. LOAD TRANSIENT RESPONSE WHEN C
For example, given R
R
L = 0.45µH, Equation 12 gives C
Assuming the compensator design is correct, Figure 14
shows the expected load transient response waveforms if
C
a square change, the output voltage V
square response.
If C
accurately represent real-time I
transient response. Figure 15 shows the load transient
response when C
upon load insertion and may create a system failure.
Figure 16 shows the transient response when C
large. V
There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU
reliability.
C
ntcs
n
n
is correctly selected. When the load current I
n
=
value is too large or too small, V
= 2.61kΩ, R
-------------------------------------------------------------- -
R
----------------------------------------- -
R
ntcnet
ntcnet
core
is sluggish in drooping to its final value.
WAVEFORMS
TOO SMALL
TOO LARGE
×
+
R
R
L
sum
sum
n
ntc
is too small. V
×
DCR
= 10kΩ, DCR = 1.1mΩ and
sum
= 3.65kΩ, R
V
V
V
i
i
i
o
o
o
o
o
o
o
n
(s) and will worsen the
core
= 0.18µF.
will sag excessively
p
Cn
core
= 11kΩ,
(s) will not
also has a
October 26, 2009
n
core
is too
(EQ. 12)
FN6924.0
n
n
has
IS
IS