z90102 ZiLOG Semiconductor, z90102 Datasheet - Page 18

• Manufacturer Part Number: z90102
• Description: 40-pin Low-cost Digital Television Controller
• Manufacturer: ZiLOG Semiconductor

FUNCTIONAL DESCRIPTION (Continued)
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Memory Mapped Register. All control registers and I/O
ports (except Port 2 and Port 3) are assigned to program
memory space. Address space FC00H contains OSD con-
trol registers, PWM output registers and Port 6 I/O regis-
ters. Two bits of the decoded AFCIN port are assigned to
Port 6 input port. LDE and LDEI instructions are required
to transfer data between the Register File and the Memory
Mapped Registers.
Register File. A total of 253 byte registers are implement-
ed in the Z8 core. Address 00H, 01H and FOH are re-
served. The register file consists of two I/O Port registers,
236 general-purpose registers and 15 control and status
registers (Figure 19). The instructions can access regis-
ters directly or indirectly with an 8-bit address field. This
also allows short 4-bit register addressing using the Reg-
ister Pointer. In the 4-bit mode, the register file is divided
into sixteen working-register groups, each occupying 16
continuous locations. The Register Pointer addresses the
starting location of the active working-register group (Fig-
ure 15).
18
Figure 15. Register File Configuration
Address
Hex
FC
FD
EF
FA
FB
FE
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FF
02
03
04
Interrupt Request Reg (IRQ)
Interrupt Priority Reg (IPR)
Interrupt Mask Reg (IMR)
Stack Pointer High (SPH)
Condition Flag (FLAGS)
Stack Pointer Low (SPL)
Port 0-1 Mode (P01M)
Register Pointer (RP)
T1 Prescaler (PRE1)
T0 Prescaler (PRE0)
Timer/Counter0 (T0)
Timer/Counter1(T1)
Timer Mode (TMR)
Port 2 Mode (P2M)
Port 3 Mode (P3M)
General-Purpose
Port 2 (P2)
Port 3 (P3)
Registers
Reserved
Note: Register Bank E0-EF is only accessed through a
working register and indirect addressing modes.
1F
10
FF
F0
2F
20
0F
00
•
•
•
•
•
•
•
•
•
•
•
Figure 16. Register Pointer
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
r7 r6 r5 r4
Register Group 1
Register Group F
Specified Working
Register Group 0
Register Group
I/O Ports
•
•
•
r3 r2 r1 r0
R253
(Register Pointer)
DS97TEL1902
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
R15 to R0
R15 to R0
R15 to R4
R3 to R0
Zilog