z90102 ZiLOG Semiconductor, z90102 Datasheet - Page 23
z90102
Manufacturer Part Number
z90102
Description
40-pin Low-cost Digital Television Controller
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z90102.pdf
(36 pages)
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Zilog
Watch-Dog Timer (WDT). The Z90102/3/4 is equipped
with a permanently enabled Watch-Dog Timer which must
be refreshed every 12 ms. Failure to refresh the timer re-
sults in a reset of the device. The WDT is permanently en-
abled and is initially reset upon POR. Every subsequent
WDT instruction resets the timer. The Watch-Dog Timer
may or may not be enabled during the STOP Mode. The
instruction WDT 4F (HEX) enables the timer during HALT.
DS97TEL1902
VBO
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
-60
Figure 21. Voltage Sensitive Reset vs Temperature
-40
-20
+0
20
If the WDH instruction is used, and if the HALT Mode is not
released and the Watch-Dog Timer is not retriggered (by
the WDT instruction) within 12 ms, a device reset occurs.
The WDT instruction affects the Z (Zero) S (Sign), and V
(Overflow) flags. WDT does not run during STOP Mode.
V
driven if V
CC
40
Voltage Sensitive Reset (VSR). Reset is globally
40-Pin Low-Cost Digital Television Controller
60
CC
is below the specified voltage (Figure 21).
80
100
Temperature
120
(°C)
Z90102/90103/90104
140
23
1
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