cy7c1386b-cy7c1387b Cypress Semiconductor Corporation., cy7c1386b-cy7c1387b Datasheet - Page 8

• Manufacturer Part Number: cy7c1386b-cy7c1387b
• Description: 512k X 36/1m X 18 Pipelined Dcd Sram
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-05195 Rev. **
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(133-MHz device).
The CY7C1386B/
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
for 1387B) inputs. A Global Write Enable (GW) overrides all
byte write inputs and writes data to all four bytes. All writes are
simplified with on-chip synchronous self-timed write circuitry.
Synchronous Chip Selects (CE
BGA) and an asynchronous OE provide for easy bank
selection and output three-state control. ADSP is ignored if
CE
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 4.2 ns (133-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
The CY7C1386B/CY7C1387B are double-cycle deselect
parts. Once the SRAM is deselected at clock rise by the chip
select and either ADSP or ADSC signals, its output will
three-state immediately after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) chip select is asserted active. The address presented is
loaded
advancement logic while being delivered to the RAM core. The
1
is HIGH.
into
the
supports secondary cache in systems
address
1
register
, CE
a,b,c,d
2
, CE
for 1386B and BW
and
3
for TQFP / CE
CO
®
the
) is 4.2 ns
and i486
address
1
a,b
for
1
Write signals (GW, BWE, and BWx) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BWx
signals. The CY7C1386B/CY7C1387B provides byte Write
capability that is described in the Write Cycle Description
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write (BW
CY7C1387B) input will selectively write to only the desired
bytes. Bytes not selected during a byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Because the CY7C1386B/CY7C1387B is a common I/O
device, the OE must be deasserted HIGH before presenting
data to the DQ inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ are automatically
three-stated whenever a Write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and
(4) the appropriate combination of the write inputs (GW, BWE,
and BWx) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented to A
into the address register and the address advancement logic
while being delivered to the RAM core. The ADV input is
ignored during this cycle. If a Global Write is conducted, the
data presented to the DQ
address location in the RAM core. If a byte Write is conducted,
only the selected bytes are written. Bytes not selected during
a byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify
Write operations.
Because the CY7C1386B/CY7C1387B is a common I/O
device, the OE must be deasserted HIGH before presenting
data to the DQ
drivers. As a safety precaution, DQ
three-stated whenever a write cycle is detected, regardless of
the state of OE.
Burst Sequences
The CY7C1386B/CY7C1387B provides a two-bit wraparound
counter, fed by A
linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel Pentium
The linear burst sequence is designed to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
[x:0]
[1:0]
inputs. Doing so will three-state the output
, that implements either an interleaved or
a,b,c,d
[x:0]
is written into the corresponding
for CY7C1386B, and BW
[x:0]
CY7C1386B
CY7C1387B
are automatically
®
[17:0]
Page 8 of 32
applications.
is loaded
a,b
for