cy7c1386b-cy7c1387b Cypress Semiconductor Corporation., cy7c1386b-cy7c1387b Datasheet - Page 9

• Manufacturer Part Number: cy7c1386b-cy7c1387b
• Description: 512k X 36/1m X 18 Pipelined Dcd Sram
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-05195 Rev. **
Interleaved Burst Sequence
Linear Burst Sequence
Sleep Mode
Address
Address
A
First
First
A
[1:0]]
00
01
10
11
00
01
10
11
[1:0]
Address
Address
Second
Second
A
A
01
00
11
10
01
10
11
00
[1:0]
[1:0]
Address
Address
Third
Third
A
A
10
00
01
10
00
01
11
11
[1:0]
[1:0]
Address
Address
Fourth
Fourth
A
A
10
01
00
00
01
10
11
11
[1:0]
[1:0]
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of t
LOW.
ZZ Mode Electrical Characteristics
I
t
t
Parameter Description
DDZZ
ZZS
ZZREC
Sleep mode
standby
current
Device
operation to
ZZ
ZZ recovery
time
ZZ > V
ZZ > V
ZZ < 0.2V
ZZREC
Conditions
Test
DD
DD
after the ZZ input returns
– 0.2V
– 0.2V
CY7C1386B
CY7C1387B
2t
Min. Max. Unit
CYC
Page 9 of 32
2t
20
CYC
mA
ns
ns