ics950402 Integrated Device Technology, ics950402 Datasheet

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... PCICLK10/HTTCLK3 11 ****PCICLK2 17 ****PCICLK3 18 ~*PCICLK_F/ModeC 23 ~*(PCICLK6)PCI_STOP# 24 Functionality FS3 48MHz 24_48MHz REF (2:0) Stop CPUCLKC (1:0) CPUCLKT (1:0) PCICLK (6:0, 11) Stop PCICLK_F PCICLK/HTTCLK (3: ICS950402 Pin Configuration *FS0/REF0 1 48 REF1/FS1* VDDREF 2 47 GND VDDREF REF2/FS2* GND 5 44 Reset# 43 VDDA 42 GND 41 CPUCLK8T0 VDDPCI 9 40 CPUCLK8C0 GND 10 ...

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... ICS950402 Pin Descriptions PIN # PIN NAME TYPE 1 *FS0/REF0 VDDREF GND 5 6 *(PCICLK7/HTTCLK0)ModeA 7 *PCICLK8/HTTCLK1/ModeB PCICLK9/HTTCLK2 8 9 VDDPCI 10 GND ~PCICLK10/HTTCLK3 11 12 PCICLK11 13 PCICLK0 PCICLK1 14 15 GND 16 VDDPCI 17 ****PCICLK2 18 ****PCICLK3 19 VDDPCI 20 GND 21 PCICLK4 22 PCICLK5 23 ~*PCICLK_F/ModeC 24 ~*(PCICLK6)PCI_STOP# 25 SCLK 26 SDATA 27 GND 28 24_48MHz/Sel24_48#*~ 29 AVDD48 30 GND ...

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... Clawhammer and Sledgehammer systems. The ICS950402 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the ...

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... ICS950402 General I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) sends the data byte count = X • ...

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... CPU HTT PCI VCO MHz MHz MHz MHz 67.27 33.63 403.60 66.95 33.48 535.60 67.20 33.60 672.00 67.33 33.67 404.00 66.80 33.40 400.80 66.75 33.38 534.00 66.68 33.34 666.80 66.80 33.40 400.80 60.00 30.00 600.00 60.00 30.00 360.00 70.00 35.00 420.00 60.00 30.00 480.00 67.50 33.75 540.00 66.67 33.33 466.66 66.67 33.33 533.34 75.00 37.50 600.00 66.67 33.33 400.00 66.67 33.33 533.32 66.66 33.33 666.64 66.67 33.33 400.00 68.67 34.33 412.00 68.66 34.33 549.32 68.66 34.33 686.64 68.67 34.33 412.00 61.80 30.90 618.00 61.80 30.90 370.80 72.10 36.05 432.60 61.80 30.90 494.40 69.53 34.76 556.20 68.67 34.33 480.66 68.67 34.33 549.34 77.25 38.63 618.00 5 ICS950402 ...

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... ICS950402 Table: Functionality and Frequency Control Register Byte 0 Pin # - Bit 7 Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit Bit Table: Output Control Register Byte 1 Pin # 7 Bit 7 PCICLK8/HTTCLK1 Bit 6 6 PCICLK7/HTTCLK0 Bit Bit 4 Bit 3 18 Bit 2 17 Bit Bit 0 ...

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... Writing to this register will configure how many BC4 bytes will be read back, BC3 default bytes. BC2 BC1 BC0 Control Name Function RID3 RID2 REVISION ID RID1 RID0 VID3 VID2 VENDOR ID VID1 VID0 7 ICS950402 Type Disable Enable RW Disable Enable ...

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... ICS950402 Table: Output Control Register Byte 8 Pin # Bit 7 - Bit Bit 5 Bit 4 - Bit Bit 2 Bit Bit Table: Watchdog Timer Register Byte 9 Pin # - Bit 7 Bit 6 - Bit 5 - Bit Bit 3 Bit 2 - Bit Bit Table: VCO Control Select Bit & WD Timer Control Register ...

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... ICS Spread % table for spread programming. SSP9 SSP8 Control Name Function PCI(9:7)/HTT(2:0) divider ratio can be configured via these 4 bits individually. CPU Div3 CPU divider ratio can be CPU Div2 configured via these 4 CPU Div1 bits individually. CPU Div0 9 ICS950402 Type ...

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... ICS950402 Table: Output Divider Control Register Byte 16 Pin # Bit 7 - Bit Bit 5 Bit 4 - Bit 3 - Bit 2 - Bit Bit 0 Table 2: CPU, HTT & PCI Divider Ratio Combination Table Bit 00 00 0000 01 0001 10 0010 11 0011 LSB Address Table: Output Divider Control Register Byte 17 ...

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... Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GSR_EN Gearshift Reset Enable ASEL Async Frequency Select AEN Async Frequency Enable 11 ICS950402 Type See Table 3: 7-Steps Skew Programming Table See Table 3: 7-Steps Skew RW Programming Table RW Type ...

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... ICS950402 Table 4: Asynchronous Fix PLL Frequency Select Table controlled by Byte 21 bits (1:0) Byte 21 Byte 21 VCO Bit 1 Bit 0 FREQ 0 0 528 0 1 Main PLL 1 0 528 1 1 Main PLL Table: Drive Strength Control Register Byte 22 Pin # Bit 7 - PCI10/HTT3 DrCntrl - Bit 6 Bit ...

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... V +/-5% (unless otherwise stated) CONDITIONS IL1 IL2 Max loads; Select @ 100MHz Max loads; Select @ 133MHz 3 Logic Inputs IN X1 & X2 pins INX From target DD frequency 13 ICS950402 +3 MIN TYP MAX 0.3 0 -200 171 250 183 600 12 14.318 16 27 ...

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... ICS950402 Electrical Characteristics - CPUCLK 70°C; V =3.3V +/- 5 PARAMETER SYMBOL Output Impedance Output High Voltage V Output Low Voltage V I Output Low Current 1 d Duty Cycle 1 Jitter, Cycle-to-cycle t jcyc-cyc2B Differential Voltage, measured @ the 1,2 Hammer test load (single-ended V DIFF 1 V measured @ the Hammer test load ...

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... L CONDITIONS Measured from 20 - 60%, 1X drive strength 2.3X drive strength Measured from 60 - 20%, 1X drive strength 2.3X drive strength Measured on rising edge @ 1. ICS950402 MIN TYP MAX UNITS 2.4 V 0 0.9 0.92 1.38 4 V/ns 1 1.63 1.15 1 1.93 4 V/ns 2. ...

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... ICS950402 Electrical Characteristics - REF 70° 3.3V +/-5 PARAMETER SYMBOL Output High Voltage V OH5 Output Low Voltage V OL5 I Output High Current OH5 I Output Low Current OL5 1 Rise Edge Rate t 1 Fall Edge Rate Duty Cycle 1 Jitter, Cycle-to-Cycle t jcyc-cyc5 1 Jitter, Accumulated 1 Guaranteed by design, not 100% tested in production ...

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... The programming resistors should be located close to the series termination resistor to minimize the current loop area more important to locate the series termination resistor close to the driver than the programming resistor. Via to VDD 2K 8.2K Clock trace to load Series Term. Res. Fig ICS950402 ...

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... ICS950402 INDEX INDEX AREA AREA Ordering Information ICS950402yGLF-T Example: ICS XXXX y G LF- T 0700B—04/30/04 c 6.10 mm. Body, 0.50 mm. Pitch TSSOP L SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS aaa - VARIATIONS SEATING SEATING ...

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... Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 19 ICS950402 In Millimeters In Inches COMMON DIMENSIONS MIN MAX MIN 2.41 2.80 .095 0.20 ...