ics950402 Integrated Device Technology, ics950402 Datasheet - Page 6

• Manufacturer Part Number: ics950402
• Description: Amd - K8 System Clock Chip
• Manufacturer: Integrated Device Technology

ICS950402
0700B—04/30/04
I
I
I
I
2
2
2
2
C Table: Functionality and Frequency Control Register
C Table: Output Control Register
C Table: Output Control Register
C Table: PCI Free-Run Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 0
Byte 1
Byte 2
Byte 3
37/36
41/40
22
21
18
17
14
13
45
48
28
31
12
11
22
21
18
17
14
13
7
6
1
8
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
PCICLK8/HTTCLK1
PCICLK7/HTTCLK0
PCICLK9/HTTCLK2
CPUT/C_1
CPUT/C_0
24_48MHz
PCICLK11
PCICLK10
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
48MHz
Name
Name
Name
Name
REF2
REF1
REF0
-
-
-
-
-
-
-
-
PCI_STOP# Control
PCI_STOP# Control
PCI_STOP# Control
PCI_STOP# Control
PCI_STOP# Control
PCI_STOP# Control
PCI_STOP# Control
PCI_STOP# Control
Write Disable S/W
Write Enable S/W
SPREAD Enable
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Function
Function
Function
Function
Control
Control
Control
Control
Control
Control
FS4
FS3
FS2
FS1
FS0
6
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
See Table1: Frequency
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
0
0
0
0
Selection Table
Free Run
Free Run
Free run
Free run
Free run
Free run
Free run
Free run
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
PWD
PWD
PWD
PWD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0