sy89533l Micrel Semiconductor, sy89533l Datasheet - Page 3

• Manufacturer Part Number: sy89533l
• Description: 3.3v, Precision, 33mhz To 500mhz Programmable Lvpecl And Lvds Bus Clock Synthesizer
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
Power
Configuration
Input/Output
M9999-110405
[e-mail] or [phone]
PIN DESCRIPTION
4, 9, 25, 63, 29
(exposed pad)
51, 52, 53, 54
17, 18, 19, 20
Pin Number
Pin Number
Pin Number
13,14,15,16
30, 31, 50
22, 23, 24
26, 27, 28
56, 57, 58
60, 61
1, 2, 3
10, 11
32–49
5, 6
62
55
21
59
12
64
4
7
8
REFCLK, /REFCLK
LOOP FILTER
FSEL_C (2:0)
FSEL_B (2:0)
FSEL_A (2:0)
OUT_SYNC
QA1 to QA0
QB8 to QB0
QC1 to QC0
LOOP REF
Pin Name
Pin Name
VCO_SEL
PSEL(1:0)
Pin Name
VBB_REF
V
V
V
V
M (3:0)
CC_Logic
V
GND
CCO
CCO
CCO
NC
NC
CCA
A
B
C
Power for Core Logic: Connect to 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
Power for PLL: Connect to “quiet” 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
Power for Output Drivers: Connect all V
connected internally on the die.
Ground. All GND pins must be tied together on the PCB. Exposed pad must be
soldered to a ground plane.
LVTTL/CMOS Compatible Input: Selects between internal or external VCO. When
tied LOW (GND) internal VCO is selected. For external VCO, leave floating (default
condition is logic HIGH). Internal 25k pull-up.
LVTTL/CMOS Compatible Input: Controls input frequency pre divider. Internal 25k
pull-up. Default is logic HIGH. See “Pre-Divide Frequency Select” table.
Analog Input/Output: Provides the reference voltage for PLL loop filter.
Analog Input/Output: Provides the loop filter for PLL. See “External Loop Filter
Considerations” for loop filter values.
LVTTL/CMOS Compatible Input: Used to change the PLL (Phase-Lock Loop)
feedback divider. Internal 25k pull-up. (M0 = LSB). Default is logic HIGH.
See “Feedback Divide Select” table.
LVTTL/CMOS Compatible Input: Bank C post divide select. Internal 25k pull-up.
Default is logic HIGH. See “Post-Divide Frequency Select” table.
LVTTL/CMOS Compatible Input: Bank B post divide select. Internal 25k pull-up.
Default is logic HIGH. See “Post-Divide Frequency Select” table.
LVTTL/CMOS Compatible Input: Bank A post divide select. Internal 25k pull-up.
Default is logic HIGH. See “Post-Divide Frequency Select.” FSEL_A0 = LSB.
Banks A,B,C output synchronous control: (LVTTL/CMOS compatible).
Internal 25k
HIGH-LOW-HIGH pulse to resynchronize all output banks.
No Connect: Leave floating.
Reference Input: This flexible input accepts any input TTL/CMOS, LVPECL, LVDS,
HSTL, SSTL. See “Input Interface” section.
Reference Output Voltage. Used for single-ended input. Maximum sink/source
current = 0.5mA.
Bank A 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_A
(0:2). Terminate outputs with 50 to V
Recommendations” section for termination detail.
Bank B Output Drivers: SY89534: 100k LVPECL output drivers.
SY89535: Differential LVDS outputs. See “Output Termination Recommendations”
section for termination detail. Output frequency is controlled by FSEL_B (0:2).
Bank C 100k LVPECL Output Drivers: Output frequency is controlled by
FSEL_C (0:2). Terminate outputs with 50 to V
Recommendations” section.
No Connect: Leave floating.
pull-up. After any bank has been programmed, toggle with a
3
Functional Description
Functional Description
Functional Description
CC
CCO
–2V. See “Output Termination
pins to 3.3V supply. V
CC
–2V. See “Output Termination
CCO
Precision Edge
pins are not
SY89534/35L
®