vsc8131 Vitesse Semiconductor Corp, vsc8131 Datasheet
vsc8131
Related parts for vsc8131
vsc8131 Summary of contents
Page 1
... Clock Outputs General Description The VSC8131 multiplexes 32 TTL compatible 77.76Mb/s Parallel Data Inputs (D0-D31) into a single LVPECL 2.488 Gb/s serial output (DO+) for use in SONET STS-48/SDH STM-16 systems. An integrated Clock Multiplier Unit (CMU) generates a LVPECL 2.488 GHz clock signal (CO+ ) from an externally supplied LVPECL compliant 77 ...
Page 2
... The timing for the low speed parallel interface is based upon the CK78OUT output signal. The intent is to have the device upstream from the VSC8131 use the CK78OUT clock signal as the timing source for its final output stage latch. CK78IN driven by CK78OUT, refer to Figure 1. This reduces the setup time of the VSC8131 ...
Page 3
... Preliminary Datasheet VSC8131 High Speed Data Output The high speed data will be multiplexed in the sequence D0 D31 with D0 being transmitted first. The high speed data output driver consists of a differential pair designed to drive a 50 transmission line should be terminated with a 100 puts, refer to Figure 2 ...
Page 4
... VSC8131 which has the REFCLK noise in addition to the intrinsic jitter from the VSC8131 itself. REFCLK is a LVPECL level and is required differential signal in order to meet the 4pS RMS jitter spec. The true and complement inputs of the differential PECL receiver are internally biased to VCC/2 so that the REFCLK signal can be AC coupled without using external bias resistors, refer to Figure 3 ...
Page 5
... Extra care needs to be taken when decoupling the analog power supply pins (labeled V maintain the optimal jitter and loop bandwidth characteristics of the PLL contained in the VSC8131, the analog power supply pins should be filtered from the main power supply with C-L-C pi filter. If preferred, a ferrite bead may be used to provide the isolation ...
Page 6
... Gbit/sec 32:1 SONET/SDH Mux with Clock Generator AC Characteristics Table 1: VSC8131 Multiplexer AC Characteristics Parameter t REFCLK period DRCLK t CK78IN period DCLK32 t CK78OUT (CLK/32) duty cycle DC32 t LOL Duty Cycle (When CMU is not locked) DCLOL t D(0-31) and PARBIT set-up time (wrt CK78IN rising edge) DSU ...
Page 7
... Preliminary Datasheet VSC8131 DC Characteristics Table 2: VSC8131 Multiplexer DC Characteristics Parameters Description V Output HIGH voltage (DO) OH(DO) V Output LOW voltage (DO) OL(DO) Output differential voltage V OD(DO) (DO) V Output common mode voltage CM(DO) V Output HIGH voltage (CO) OH(CO) V Output LOW voltage (CO) OL(CO) Output differential voltage V OD(CO) (CO) V Output common mode voltage CM(CO) Back Termination Impedance ...
Page 8
... Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. ESD Ratings Proper ESD procedures should be used when handling this product. The VSC8131 is rated to 1500V based on the human body model. Page 8 741 Calle Plano, Camarillo, CA 93012 • ...
Page 9
... Preliminary Datasheet VSC8131 Figure 5: Parametric Measurement Information G52249-0, Rev. 3.0 11/9/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION 32:1 SONET/SDH Mux with Clock Generator TTL Rise and Fall Time Parametric Test Load Circuit Serial Output Load ...
Page 10
... Serialized Data, compliment PWR +3. Leave Unconnected PWR +3.3V PWR +3.3V PWR +3.3V PWR GND PWR GND PWR GND PWR GND PWR GND - - Leave Unconnected - - Leave Unconnected - - Leave Unconnected - - Leave Unconnected - - Leave Unconnected - - Leave Unconnected VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC8131 Pin Description G52249-0, Rev. 3.0 11/9/99 ...
Page 11
... Preliminary Datasheet VSC8131 Table 4: Package Pin Identification Signal Pin VCC 39 VEE VEE 42 VCC LOL 49 VCC 50 VEE 51 PARERR 52 CK78OUT 53 VCC 54 CK78IN VEE 57 D31 58 D30 59 VCC 60 D29 61 D28 VCC VCC 66 D27 67 D26 ...
Page 12
... I TTL parallel data PWR +3.3V I TTL parallel data I TTL parallel data PWR +3.3V PWR +3. Leave Unconnected I TTL parallel data I TTL parallel data PWR +3.3V I TTL parallel data I TTL parallel data PWR GND VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC8131 Pin Description (MSB) G52249-0, Rev. 3.0 11/9/99 ...
Page 13
... Preliminary Datasheet VSC8131 Table 4: Package Pin Identification Signal Pin PARBIT 111 PARMODE 112 VCC 113 TEST 114 NC 115 REFCLK+ 116 REFCLK- 117 VCC 118 VEE 119 TEST 120 TEST 121 VEE_ANA 122 VCC_ANA 123 NC 124 NC 125 VEE 126 VEE 127 VCC 128 Connection ...
Page 14
... Figure 6: 128 PQFP Package Drawing PIN 102 RAD. 2.92 .50 ( 2.54 .50 PIN TOP VIEW STANDOFF .25 b 0.17 MAX. LEAD COPLANARITY L VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC8131 Key mm Tolerance A 2.35 MAX A1 0.25 MAX A2 2.00 +.10 D 17.20 ±.20 D1 14.00 ±.10 E 23.20 ±.20 E1 20.00 ±.10 L ...
Page 15
... The worst case ambient temperature without use of a heatsink is given by the equation: where: Ambient Air temperature A(MAX) Case temperature (85 C(MAX ) P Power (2.15W for VSC8131) (MAX) Theta case to ambient at appropriate airflow CA The results of this calculation are listed below: G52249-0, Rev. 3.0 11/9/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 ...
Page 16
... Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. Page 16 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION o C 33.2 42.4 49.1 53.6 57.1 VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet VSC8131 G52249-0, Rev. 3.0 11/9/99 ...