vsc8131 Vitesse Semiconductor Corp, vsc8131 Datasheet - Page 4

• Manufacturer Part Number: vsc8131
• Description: 2.488 Gbit/sec 32 1 Sonet/sdh Mux With Clock Generator
• Manufacturer: Vitesse Semiconductor Corp

2.488 Gbit/sec
32:1 SONET/SDH Mux with Clock Generator
Page 4
Clock Generator
REFCLK input. The on-chip PLL uses a low phase noise reactance based Voltage Controlled Oscillator (VCO)
with an on-chip loop filter. The loop bandwidth of the PLL is within the SONET specified limit of 2MHz. The
REFCLK is 77.76MHz and should be of high quality. Noise on the REFCLK below the loop band width of the
PLL will pass through the PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a
VCXO may be required to avoid passing REFCLK noise with greater than 4ps RMS of jitter to the output. Such
a condition would create an output from the VSC8131 which has the REFCLK noise in addition to the intrinsic
jitter from the VSC8131 itself. REFCLK is a LVPECL level and is required to be a differential signal in order to
meet the 4pS RMS jitter spec. The true and complement inputs of the differential PECL receiver are internally
biased to VCC/2 so that the REFCLK signal can be AC coupled without using external bias resistors, refer to
Figure 3. REFCLK can be DC coupled by simply over-driving the internal bias voltage.
Loss of Lock
reported when the CMU does not lock to the REFCLK frequency or when the REFCLK input signal is not
present. LOL is high when the CMU is locked. LOL is low when the REFCLK input signal is not present (input
floating due to cut line or input stuck high or low). The LOL signal will appear as a pulse train of 1’s and 0’s
when the REFCLK is present, but the CMU is not locked to the REFCLK’s frequency. The frequency of the
LOL pulse train can be anywhere from 500Hz to 50MHz.
An on-chip Phase Locked Loop (PLL) generates the 2.488 GHz transmit clock from the externally provided
The Loss Of Lock (LOL) output is used to indicate if the CMU is locked. A loss of lock condition is
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
INPUT
INPUT
Figure 3: REFCLK Internal Bias Configuration
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
V
CC
V
= +3.3V
EE
= 0V
V
V
CC
2
CC
2
All Resistors
3.3K
Preliminary Datasheet
VSC8131
G52249-0, Rev. 3.0
11/9/99