cy7b9945v Cypress Semiconductor Corporation., cy7b9945v Datasheet - Page 3

• Manufacturer Part Number: cy7b9945v
• Description: High-speed Multi-phase Pll Clock Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07336 Rev. *E
Block Diagram Description
The PLL adjusts the phase and the frequency of its output
signal to minimize the delay between the reference (REFA/B+,
REFA/B-) and the feedback (FB) input signals.
The CY7B9945V has a flexible REF input scheme. These
inputs allow the use of either differential LVPECL or
single-ended LVTTL inputs. To configure as single-ended
nally pulled to 1.5V), then the other input pin can be used as
a LVTTL input. The REF inputs are also tolerant to hot
insertion.
The REF inputs can be changed dynamically. When changing
from one reference input to the other reference input of the
same frequency, the PLL is optimized to ensure that the clock
outputs period will not be less than the calculated system
budget (t
(cycle-cycle jitter) – t
reacquiring lock.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (f
device. f
setting for the device is shown in Table 1. For CY7B9945V, the
upper f
Table 1. Frequency Range Select
Time Unit Definition
Selectable skew is in discrete increments of time unit (t
value of a t
nominal output frequency. The equation to be used to
determine the t
t
N is a multiplication factor which is determined by the FS
setting. f
in Table 2.
Table 2. N Factor Determination
Divide and Phase Select Matrix
The Divide Select Matrix is comprised of three independent
banks: two banks of clock outputs and one bank for feedback.
The Phase Select Matrix, on the other hand, enables
independent phase adjustments on 1Q[0:1], 1Q[2:3] and
2Q[0:5]. The frequency of 1Q[0:3] is controlled by 1DS[0:1]
while the frequency of 2Q[0:5] is controlled by 2DS[0:1]. The
Notes:
LVTTL inputs, the complementary pin must be left open (inter-
LOW
MID
HIGH
LOW
MID
HIGH
U
1.
2.
= 1/(f
FS
The level to be set on FS is determined by the “nominal” operating frequency (f
the output is operating in the undivided mode. The REF and FB are at f
BK1Q denotes following the skew setting of indicated Bank1 outputs.
FS
NOM
NOM
NOM
[1]
NOM
MIN
U
range extends from 96 MHz to 200 MHz.
*N).
is determined by the FS setting and the maximum
is directly related to the VCO frequency. The FS
is nominal frequency of the device. N is defined
= t
U
32
16
N
8
value is as follows:
REF
PDEV
(nominal reference period) – t
Min.
f
24
48
96
NOM
(max. period deviation)) while
CY7B9945V
(MHz) at which t
f
NOM
(MHz)
31.25
62.5
125
Max.
100
200
52
U
NOM
= 1.0 ns
) of the
U
). The
CCJ
NOM
when the output connected to FB is undivided.
NOM
phase of 1Q[0:1] is controlled by 1F[0:1], that of 1Q[2:3] is
controlled by 1F[2:3] and that of 2Q[0:5] is controlled by
2F[0:1].
The high-fanout feedback output buffer (QF) may connect to
the feedback input (FBK). This feedback output also has one
phase function select input (FBF0) and two divider function
selects FBDS[0:1].
The phase capabilities that are chosen by the phase function
select pins are shown in Table 3. The divide capabilities for
each bank are shown in Table 4.
Table 3. Output Phase Select
Table 4. Output Divider Select
Figure 1 illustrates the timing relationship of programmable
skew outputs. All times are measured with respect to REF with
the output used for feedback programmed with 0t
PLL naturally aligns the rising edge of the FB input and REF
input. If the output used for feedback is programmed to
another skew position, then the whole t
respect to REF. For example, if the output used for feedback
is programmed to shift –4t
forward in time by 4t
of skew will effectively be skewed 8t
and FBDS1
Control Signal
HIGH
HIGH
HIGH
[1:2]DS1
LOW
LOW
LOW
) of the V
1F1
1F3
2F1
MID
MID
MID
HIGH
HIGH
HIGH
LOW
LOW
LOW
MID
MID
MID
Control Signal
CO
FBF0
HIGH
HIGH
HIGH
LOW
LOW
LOW
and Phase Generator. f
MID
1F0
1F2
2F0
MID
MID
[1:2]DS0
FBDS0
HIGH
HIGH
HIGH
LOW
LOW
LOW
MID
MID
MID
and
1Q[0:1]
U
–4t
–3t
–2t
–1t
+1t
+2t
+3t
+4t
. Thus an output programmed with 4t
0t
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Bank1
Output Phase Function
, then the whole matrix is shifted
/ 10
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/ 1
/ 2
/ 3
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Output Divider Function
NOM
1Q[2:3]
–4t
–3t
–2t
–1t
+1t
+2t
+3t
+4t
0t
always appears on an output when
U
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with respect to REF.
Bank2
RoboClock
U
/ 10
/ 12
CY7B9945V
BK1Q[0:1]
BK1Q[2:3]
/ 1
/ 2
/ 3
/ 4
/ 5
/ 6
/ 8
matrix will shift with
2Q[0:5]
+6t
+7t
+8t
–8t
–7t
–6t
0t
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Page 3 of 10
U
Feedback
[2]
[2]
skew. The
/ 10
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/ 1
/ 2
/ 3
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/ 5
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+4t
–4t
N/A
N/A
N/A
N/A
N/A
N/A
0t
QF

U
U
U
U
[+] Feedback