cy7b9945v Cypress Semiconductor Corporation., cy7b9945v Datasheet - Page 5

• Manufacturer Part Number: cy7b9945v
• Description: High-speed Multi-phase Pll Clock Buffer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07336 Rev. *E
Lock Detect Output Description
The LOCK detect output indicates the lock condition of the
integrated PLL. Lock detection is accomplished by comparing
the phase difference between the reference and feedback
inputs. Phase error is declared when the phase difference
between the two inputs is greater than the specified device
propagation delay limit t
When in the locked state, after four or more consecutive
feedback clock cycles with phase-errors, the LOCK output will
be forced LOW to indicate out-of-lock state.
When in the out-of-lock state, 32 consecutive phase-errorless
feedback clock cycles are required to allow the LOCK output
to indicate lock condition (LOCK = HIGH).
f the feedback clock is removed after LOCK has gone HIGH,
a “Watchdog” circuit is implemented to indicate the out-of-lock
condition after a time-out period by deasserting LOCK LOW.
This time out period is based upon a divided down reference
clock.
This assumes that there is activity on the selected REF input.
If there is no activity on the selected REF input then the LOCK
detect pin may not accurately reflect the state of the internal
PLL.
Factory Test Mode Description
The device will enter factory test mode when the MODE is
driven to MID. In factory test mode, the device will operate with
its internal PLL disconnected; input level supplied to the
reference input will be used in place of the PLL output. In TEST
mode the FB input must be tied LOW. All functions of the
device are still operational in factory test mode except the
internal PLL and output bank disables. The MODE input is
designed to be a static input. Dynamically toggling this input
from LOW to HIGH may temporarily cause the device to go
into factory test mode (when passing through the MID state).
When in the test mode, the device can be reset to a determin-
istic state by driving the DIS2 input HIGH. Doing so will cause
all outputs to disable and after the selected reference clock pin
has five positive transitions, all internal finite state machines
(FSM) to be set a deterministic state. The states will depend
PD
.
on the configurations of the divide, skew and frequency
selection. All clock outputs will stay in High-Z mode and all
FSMs will stay in the deterministic state until DIS2 is
deasserted, which will cause the device to reenter factory test
mode.
Safe Operating Zone
Figure 2 illustrates the operating condition at which the device
does not exceed its allowable maximum junction temperature
of 150°C. Figure 2 shows the maximum number of outputs that
can operate at 185 MHz (with 25-pF load and no air flow) or
200 MHz (with 10-pF load and no air flow) at various ambient
temperatures. At the limit line, all other outputs are configured
to divide-by-two (i.e., operating at 92.5 MHz) or lower
frequencies. The device will operate below maximum
allowable junction temperature of 150°C when its configu-
ration (with the specified constraints) falls within the shaded
region (safe operating zone). Figure 2 shows that at 85°C, the
maximum number of outputs that can operate at 200 MHz is 6.
100
95
90
85
80
75
70
65
60
55
50
Figure 2. Typical Safe Operating Zone
2
Number of Outputs at 185 MHz
Typical Safe Operating Zone
(25-pF Load, 0-m/s air flow)
Safe Operating Zone
4
6
8
RoboClock
CY7B9945V
10
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