max9796 Maxim Integrated Products, Inc., max9796 Datasheet - Page 19

• Manufacturer Part Number: max9796
• Description: Max9796 2.3w, High-power Class D Audio Subsystem With Directdrive Headphone Amplifiers
• Manufacturer: Maxim Integrated Products, Inc.

The MAX9796 features an I
consisting of a serial-data line (SDA) and a serial-clock
line (SCL). SDA and SCL facilitate communication
between the MAX9796 and the master at clock rates up
to 400kHz. Figure 7 shows the 2-wire interface timing
diagram. The MAX9796 is a receive-only slave device
relying on the master to generate the SCL signal. The
master, typically a microcontroller, generates SCL and
initiates data transfer on the bus. The MAX9796 cannot
write to the SDA bus except to acknowledge the receipt
of data from the master. The MAX9796 does not
acknowledge a read command from the master.
A master device communicates to the MAX9796 by
transmitting the proper address followed by the data
word. Each transmit sequence is framed by a START (S)
or REPEATED START (Sr) condition and a STOP (P) con-
dition. Each word transmitted over the bus is 8 bits long
and is always followed by an acknowledge clock pulse.
The MAX9796 SDA line operates as both an input and
an open-drain output. A pullup resistor, greater than
500Ω, is required on the SDA bus. The MAX9796 SCL
line operates as an input only. A pullup resistor, greater
than 500Ω, is required on SCL if there are multiple mas-
ters on the bus, or if the master in a single-master sys-
tem has an open-drain SCL output. Series resistors in
line with SDA and SCL are optional. Series resistors
protect the digital inputs of the MAX9796 from high-
voltage spikes on the bus lines, and minimize crosstalk
and undershoot of the bus signals.
Figure 7. 2-Wire Serial-Interface Timing Diagram
SDA
SCL
t
HD, STA
2.3W, High-Power Class D Audio Subsystem
CONDITION
START
______________________________________________________________________________________
with DirectDrive Headphone Amplifiers
t
LOW
t
R
2
C 2-wire serial interface
t
t
SU, DAT
HIGH
t
F
I
2
t
C Interface
HD, DAT
t
SU, STA
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I
A master device initiates communication by issuing a
START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is a
low-to-high transition on SDA while SCL is high (Figure
8). A START condition from the master signals the
beginning of a transmission to the MAX9796. The mas-
ter terminates transmission and frees the bus by issu-
ing a STOP condition. The bus remains active if a
REPEATED START condition is generated instead of a
STOP condition.
Figure 8. START, STOP, and REPEATED START Conditions
2
CONDITION
REPEATED
C bus is not busy.
START
SDA
SCL
t
HD, STA
S
t
SP
START and STOP Conditions
t
SU, STO
Sr
CONDITION
STOP
t
BUF
Bit Transfer
CONDITION
START
P
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