max9796 Maxim Integrated Products, Inc., max9796 Datasheet - Page 20

• Manufacturer Part Number: max9796
• Description: Max9796 2.3w, High-power Class D Audio Subsystem With Directdrive Headphone Amplifiers
• Manufacturer: Maxim Integrated Products, Inc.

The MAX9796 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition.
The MAX9796 is available with one preset slave
address (see Table 1). The address is defined as the
seven most significant bits (MSBs) followed by the
read/write (R/W) bit. The address is the first byte of
information sent to the MAX9796 after the START condi-
tion. The MAX9796 is a slave device only capable of
being written to. The R/W bit should be a zero when
configuring the MAX9796.
The acknowledge bit (ACK) is a clocked 9
MAX9796 uses to handshake receipt of each byte of
data (see Figure 9). The MAX9796 pulls down SDA dur-
ing the master-generated 9
ACK allows for detection of unsuccessful data transfers.
An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault has occurred. In the
2.3W, High-Power Class D Audio Subsystem
with DirectDrive Headphone Amplifiers
Table 1. MAX9796 Address Map
Figure 9. Acknowledge
Table 2. Control Registers
20
Input Mode Control
Mono Volume Control
Left Volume Control
Right Volume Control
Output Mode Control
Global Control Register
SDA
SCL
CONDITION
START
______________________________________________________________________________________
A6
1
FUNCTION
1
A5
0
2
th
NOT ACKNOWLEDGE
B7
0
0
0
0
1
1
Early STOP Conditions
clock pulse. Monitoring
ACKNOWLEDGE
A4
COMMAND
0
8
ACKNOWLEDGMENT
CLOCK PULSE FOR
B6
0
0
1
1
0
0
Slave Address
Acknowledge
th
bit that the
9
B5
0
1
0
1
0
1
A3
SLAVE ADDRESS
1
MONO+6dB
INA+20dB
SHDN
event of an unsuccessful data transfer, the bus master
may reattempt communications.
A write to the MAX9796 includes transmission of a
START condition, the slave address with the R/W bit set
to 0 (Table 1), one byte of data to configure the
Command Register, and a STOP condition. Figure 10
illustrates the proper format for one frame.
The MAX9796 only accepts write data, but it acknowl-
edges the receipt of the address byte with the R/W bit
set high. The MAX9796 does not write to the SDA bus
in the event that the R/W bit is set high. Subsequently,
the master reads all 1’s from the MAX9796. Always set
the R/W bit to zero to avoid this situation.
The MAX9796 is programmed through six control regis-
ters. Each register is addressed by the three MSBs
(B5–B7) followed by five configure bits (B0–B4) as
shown in Table 2. Correct programming of the MAX9796
requires writing to all six control registers. Upon power-
on, their default settings are as listed in Table 3.
Figure 10. Write Data Format Example
B4
ACKNOWLEDGE FROM MAX9796
A2
COMMAND BYTE IS STORED ON
S
1
RECEIPT OF STOP CONDITION
SLAVE ADDRESS
IN+6dB
B3
MVOL (Table 7)
LVOL (Table 7)
RVOL (Table 7)
A1
R/W
0
Programming the MAX9796
INMODE (Tables 5a and 5b)
DATA
0
OUTMODE (Table 9)
ACK
MUTE
B7 B6 B5 B4 B3 B2
COMMAND BYTE
B2
A0
1
FROM MAX9796
ACKNOWLEDGE
Write Data Format
SSM
B1
B1 B0
R/W
ACK
MONO
0
B0
P