max9247etmt Maxim Integrated Products, Inc., max9247etmt Datasheet - Page 14

• Manufacturer Part Number: max9247etmt
• Description: Max9247 27-bit, 2.5mhz-to-42mhz Dc-balanced Lvds Serializer
• Manufacturer: Maxim Integrated Products, Inc.

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
The MAX9247 has an integrated 100Ω output-termina-
tion resistor. This resistor damps reflections from
induced noise and mismatches between the transmis-
sion line impedance and termination resistors at the
deserializer input. With PWRDWN = low or with the sup-
ply off, the output termination is switched out and the
LVDS output is high impedance.
The integrated 100Ω output termination is made up of
two 50Ω resistors in series. The junction of the resistors
is connected to the CMF pin for connecting an optional
common-mode filter capacitor. Connect the filter
capacitor to ground close to the MAX9247 as shown in
Figure 15. The capacitor shunts common-mode switch-
ing current to ground to reduce EMI.
Figure 14. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to 42MHz
Figure 15. Common-Mode Filter Capacitor Connection
14
______________________________________________________________________________________
140
120
100
80
60
40
20
0
18
vs. PARALLEL CLOCK FREQUENCY
AC-COUPLING CAPACITOR VALUE
21
PARALLEL CLOCK FREQUENCY (MHz)
24
FOUR CAPACITORS PER LINK
TWO CAPACITORS PER LINK
27
30
Common-Mode Filter
R
R
O
O
/ 2
/ 2
33
36
OUT+
CMF
OUT-
39
Termination
42
C
CMF
The MAX9247 features a preemphasis mode where extra
current is added to the output and causes the ampli-
tude to increase by 40% to 50% at the transition point.
Preemphasis helps to get a faster transition, better eye
diagram, and improve signal integrity. See the Typical
Operating Characteristics. The additional current is
turned on for a short time (360ps, typ) during data transi-
tion, and then turned off. Enable preemphasis by driving
PRE high.
Driving PWRDWN low stops the PLL, switches out the
integrated 100Ω output termination, and puts the output
in high impedance to ground and differential. With
PWRDWN ≤ 0.3V and all LVTTL/LVCMOS inputs ≤ 0.3V or
≥ V
Driving PWRDWN high starts PLL lock to PCLK_IN and
switches in the 100Ω output termination resistor. The
LVDS output is not driven until the PLL locks. The LVDS
output is high impedance to ground and 100Ω differen-
tial. The 100Ω integrated termination pulls OUT+ and
OUT- together while the PLL is locking so that V
If V
outputs are high impedance to ground and differential.
The PLL lock time is set by an internal counter. The lock
time is 17,100 PCLK_IN cycles. Power and clock should
be stable to meet the lock-time specification.
The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0],
DE_IN, RNG0, RNG1, PRE, PCLK_IN, and PWRDWN)
are powered from V
1.71V to 3.6V supply, allowing logic inputs with a nomi-
nal swing of V
when power is applied to V
and PWRDWN is internally driven low, putting the
device in the power-down state.
The MAX9247 has isolated on-chip power domains. The
digital core supply (V
(V
The PLL has separate power and ground (V
PLLGND) and the LVDS input also has separate power
and ground (V
isolated by diode connections. Bypass each V
V
mount ceramic 0.1µF and 0.001µF capacitors in parallel
as close to the device as possible, with the smallest value
capacitor closest to the supply pin.
CCPLL
CCIN
CCIN
CC
= 0, the output resistor is switched out and the LVDS
) are isolated but have a common ground (GND).
, and V
Power-Supply Circuits and Bypassing
- 0.3V, supply current is reduced to 50µA or less.
LVDS Output Preemphasis (PRE)
CCLVDS
CCLVDS
CCIN
CCIN
. If no power is applied to V
Power-Down and Power-Off
CC
and LVDSGND). The grounds are
pin with high-frequency, surface-
) and single-ended input supply
. V
CCIN
CC
Input Buffer Supply
, the inputs are disabled
can be connected to a
PLL Lock Time
CCPLL
CC
OD
, V
= 0V.
CCIN
CCIN
and
,