max9247etmt Maxim Integrated Products, Inc., max9247etmt Datasheet - Page 6

• Manufacturer Part Number: max9247etmt
• Description: Max9247 27-bit, 2.5mhz-to-42mhz Dc-balanced Lvds Serializer
• Manufacturer: Maxim Integrated Products, Inc.

27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
6
11, 12, 15–21
1, 13, 37
_______________________________________________________________________________________
39–48
14, 38
30, 31
3–10,
PIN
22
23
24
25
26
27
28
29
32
33
34
35
36
EP
2
RGB_IN10–
CNTL_IN2–
RGB_IN17,
CNTL_IN0,
CNTL_IN1,
RGB_IN0–
CNTL_IN8
LVDSGND
PWRDWN
RGB_IN9
PCLK_IN
V
PLLGND
V
NAME
V
DE_IN
OUT+
CCLVDS
RNG1
RNG0
OUT-
GND
GND
CCPLL
CMF
PRE
V
I.C.
CCIN
CC
Input Buffer Supply and Digital Supply Ground
Input Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded
into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to
GND.
LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN
when DE_IN is low. Internally pulled down to GND.
Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Data-Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low
selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally
pulled down to GND.
LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL
reference clock. Internally pulled down to GND.
Internally Connected. Leave floating for normal operation.
Preemphasis Enable Input. Drive PRE high to enable preemphasis.
PLL Supply Ground
PLL Supply Voltage. Bypass to PLLGND with 0.1µF and 0.001µF capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter
common-mode switching noise.
LVDS Supply Ground
Inverting LVDS Serial-Data Output
Noninverting LVDS Serial-Data Output
LVDS Supply Voltage. Bypass to LVDSGND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
Exposed Pad (TQFN Package Only). Connect to GND.
FUNCTION
Pin Description