pcf8534a NXP Semiconductors, pcf8534a Datasheet - Page 13

• Manufacturer Part Number: pcf8534a
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8534A_3
Product data sheet
7.5.1 Internal clock
7.5.2 External clock
7.5 Oscillator
7.6 Timing
7.7 Display register
7.8 Segment outputs
The internal logic and the LCD drive signals of the PCF8534A are timed by the frequency
f
f
The internal oscillator is enabled by connecting pin OSC to pin V
output from pin CLK is the clock signal for any cascaded PCF8534A in the system. After
power-on, SDA must be HIGH to guarantee that the clock starts.
Connecting pin OSC to V
external clock input. A clock signal must always be applied to the device, removing the
clock can freeze the LCD in a DC state.
The timing of the PCF8534A sequences the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between all the PCF8534As in the system. The timing also generates the
LCD frame frequency which is derived as an integer division of the clock frequency
(see
the internal clock or the frequency applied to pin CLK.
Table 6.
The display register holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display register, the
LCD segment outputs and one column of the display RAM.
The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected
directly to the LCD. The segment output signals are generated based on the multiplexed
backplane signals and with data resident in the display register. When less than
60 segment outputs are required the unused segment outputs must be left open-circuit.
Frame frequency
clk
clk(ext)
f
fr
, which equals either the built-in oscillator frequency f
=
Table
. The clock frequency f
---------
f
24
clk
LCD frame frequencies
6). When an external clock is used, the frame frequency is a fixed division of
Rev. 03 — 10 November 2008
DD
enables an external clock source. Pin CLK becomes the
Nominal frame frequency (Hz)
64
clk
determines the LCD frame frequency (f
Universal LCD driver for low multiplex rates
osc
or the external clock frequency
SS
. In this case, the
PCF8534A
fr
© NXP B.V. 2008. All rights reserved.
).
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