pcf8534a NXP Semiconductors, pcf8534a Datasheet - Page 21

• Manufacturer Part Number: pcf8534a
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8534A_3
Product data sheet
8.2 I
Two I
The least significant bit of the slave address is bit R/W. The PCF8534A is a write-only
device. It will not respond to a read access, so this bit should always be logic 0. The
second bit of the slave address is defined by the level tied at input SA0. Two displays
controlled by PCF8534A can be recognized on the same I
The I
condition (S) from the I
slave addresses. All PCF8534As with the same SA0 level acknowledge in parallel to the
slave address. All PCF8534As with the alternative SA0 level ignore the whole I
transfer.
After acknowledgement, the control byte is sent defining if the next byte is RAM or
command information. The control byte also defines if the next byte is a control byte or
further RAM/command data (see
configure the device and then fill the display RAM with little overhead.
Table 8.
The command bytes and control bytes are also acknowledged by all addressed
PCF8534As connected to the bus.
The display bytes are stored in the display RAM at the address specified by the data
pointer and the subaddress counter. Both data pointer and subaddress counter are
automatically updated.
The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed
PCF8534A. After the last display byte, the I
Alternatively a START may be issued to RESTART I
Bit
7
6
5 to 0
2
Fig 16. Control byte format
•
•
C-bus protocol
Up to 16 PCF8534As on the same I
The use of two types of LCD multiplex on the same I
2
2
C-bus protocol is shown in
C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8534A.
Symbol
CO
RS
-
Load data pointer command bit description
Value
0
1
0
1
Rev. 03 — 10 November 2008
2
C-bus master which is followed by one of the available PCF8534A
MSB
CO
7
Figure
Figure 16
Description
continue bit
register selection
not relevant
RS
6
last control byte
control bytes continue
command register
data register
5
2
17. The sequence is initiated with a START
C-bus for very large LCD applications
Universal LCD driver for low multiplex rates
4
2
and
C-bus master issues a STOP condition (P).
not relevant
3
Table
2
2
C-bus access.
1
8). In this way it is possible to
mgl753
2
C-bus
0
2
LSB
C-bus which allows:
PCF8534A
© NXP B.V. 2008. All rights reserved.
2
C-bus
21 of 44