max5952auaxt Maxim Integrated Products, Inc., max5952auaxt Datasheet - Page 27

• Manufacturer Part Number: max5952auaxt
• Description: Max5952 High-power, Quad, Pse Controller For Power-over-ethernet
• Manufacturer: Maxim Integrated Products, Inc.

The power event register (Table 8) records changes in
the power status of the four ports. Any change in
PGOOD_ (R10h[7:4]) sets PG_CHG_ to 1. Any change
in the PWR_EN_ (R10h[3:0]) sets PWEN_CHG_ to 1.
PG_CHG_ and PWEN_CHG_ trigger on the edges of
PGOOD_ and PWR_EN_ and do not depend on the
DET_END_/CL_END_ is set high whenever detection/
classification is completed on the corresponding port. A
1 in any of the CL_END_ bits forces R00h[4] to 1. A 1 in
any of the DET_END_ bits forces R00h[3] to 1. As with
any of the other events register, the detect event regis-
Table 8. Power Event Register
Table 9. Detect Event Register
PG_CHG4
PG_CHG3
PG_CHG2
PG_CHG1
PWEN_CHG4
PWEN_CHG3
PWEN_CHG2
PWEN_CHG1
CL_END4
CL_END3
CL_END2
CL_END1
DET_END4
DET_END3
DET_END2
DET_END1
SYMBOL
SYMBOL
ADDRESS =
ADDRESS =
______________________________________________________________________________________
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
R/W
R/W
02h
04h
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
High-Power, Quad, PSE Controller
R/W
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
R/W
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
03h
05h
Classification completed on port 4
Classification completed on port 3
Classification completed on port 2
Classification completed on port 1
Detection completed on port 4
Detection completed on port 3
Detection completed on port 2
Detection completed on port 1
PGOOD change event for port 4
PGOOD change event for port 3
PGOOD change event for port 2
PGOOD change event for port 1
Power enable change event for port 4
Power enable change event for port 3
Power enable change event for port 2
Power enable change event for port 1
for Power-Over-Ethernet
actual level of the bits. The power event register has
two addresses. When read through the R02h address,
the content of the register is left unchanged. When read
through the CoR R03h address, the register content is
cleared. A reset sets R02h/R03h = 00h.
ter has two addresses. When read through the R04h
address, the content of the register is left unchanged.
When read through the CoR R05h address, the register
content is cleared. A reset sets R04h/R05h = 00h.
DESCRIPTION
DESCRIPTION
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