max5952auaxt Maxim Integrated Products, Inc., max5952auaxt Datasheet - Page 42

• Manufacturer Part Number: max5952auaxt
• Description: Max5952 High-power, Quad, Pse Controller For Power-over-ethernet
• Manufacturer: Maxim Integrated Products, Inc.

High-Power, Quad, PSE Controller
for Power-Over-Ethernet
Table 37. Register Summary
42
INTERRUPTS
00h
01h
EVENTS
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
STATUS
0Ch
0Dh
0Eh
0Fh
10h
11h
CONFIGURATION
12h
13h
14h
15h
16h
17h
PUSHBUTTONS
18h
19h
1Ah
GENERAL
1Bh
1Ch
1Dh
1EH
1FH
ADDR
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Port 1 Status
Port 2 Status
Port 3 Status
Port 4 Status
Power Status
Pin Status
Operating Mode
Disconnect Enable
Det/Class Enable
Backoff Enable
Timing Config
Misc Config 1
Reserved
Power Enable
Global
ID
SMODE Register
Reserved
Watchdog Register
Switch Mode
Register
Interrupt
Int Mask
Power Event
Power Event CoR
Detect Event
Detect Event CoR
Fault Event
Fault Event CoR
Tstart Event
Tstart Event CoR
Supply Event
Supply Event CoR
REGISTER NAME
R/W
CoR
CoR
CoR
CoR
CoR
CoR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO
WO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
PORT
4321
4321
4321
4321
4321
4321
4321
4321
4321
4321
4321
4321
4321
G
G
G
G
G
G
G
G
G
G
1
2
3
4
EN_WHDOG
CLASS_EN4
ID_CODE[4]
PWR_OFF4
WDTIME[7]
PG_CHG4
LD_DISC4
CL_END4
ACD_EN4
Reserved
Reserved
Reserved
Reserved
PGOOD4
Reserved
Reserved
Reserved
SUP_FLT
CLR_INT
RSRT[1]
INT_EN
MASK7
P4_M1
BIT 7
IVC4
TSD
—
—
CLASS_EN3
ID_CODE[3]
WD_INT_EN
PWR_OFF3
WDTIME[6]
CLASS1[2]
CLASS2[2]
CLASS3[2]
CLASS4[2]
PG_CHG3
LD_DISC3
TSTR_FLT
ACD_EN3
CL_END3
Reserved
RSRT_EN
Reserved
Reserved
Reserved
PGOOD3
VDD_OV
RSRT[0]
MASK6
P4_M0
BIT 6
IVC3
—
—
CLASS_EN
PWR_OFF2 PWR_OFF1
ID_CODE[ 2] ID_CODE[ 1] ID_ CODE[ 0]
WDTIME[5] WDTIME[4]
CLASS1[1]
CLASS2[1]
CLASS3[1]
CLASS4[1]
TSTART[1]
PG_CHG2
LD_DISC2
IMAX_FLT
ACD_EN2
CL_END2
PGOOD2
Reserved
Reserved
Reserved
Reserved
VDD_UV
reserved
MASK5
P3_M1
BIT 5
IVC2
A3
—
—
CLASS_EN
VEE_UVLO
CLASS1[0]
CLASS2[0]
CLASS3[0]
CLASS4[0]
TSTART[0]
PG_CHG1
LD_DISC1
ACD_EN1
RESET_IC
CL_END1
PGOOD1
Reserved
Reserved
Reserved
CL_END
MASK4
P3_M0
CSCM
BIT 4
IVC1
A2
—
—
IMAX_FLT4
STRT_FLT4
WDTIME[3]
HWMODE4
DET_END4
TFAULT[1]
PWR_ON4
RESET_P4
DET_END
PWR_EN4
DCD_EN4
BCKOFF4
Reserved
Reserved
Reserved
Reserved
POFF_CL
Reserved
Reserved
DET_EN4
SMODE4
VEE_OV
MASK3
PWEN_
P2_M1
CHG4
BIT 3
A1
DET_ST1[2] DET_ST1[1]
DET_ST2[2] DET_ST2[1]
DET_ST3[2] DET_ST3[1]
DET_ST4[2] DET_ST4[1]
IMAX_FLT3
STRT_FLT3
WDTIME[2]
HWMODE3
DET_END3
TFAULT[0]
PWR_ON3
RESET_P3
PWR_EN3
DCD_EN3
BCKOFF3
Reserved
Reserved
DET_EN3
LD_DISC
CL_DISC
SMODE3
VEE_UV
MASK2
PWEN_
REV [2]
P2_M0
CHG3
BIT 2
A0
IMAX_FLT2
STRT_FLT2
WDTIME[1]
HWMODE2
DET_END2
OSC_FAIL
PWR_ON2
RESET_P2
PWR_EN2
MIDSPAN
DCD_EN2
BCKOFF2
Reserved
Reserved
DET_EN2
TDISC[1]
OUT_ISO
SMODE2
PG_INT
MASK1
PWEN_
REV [1]
P1_M1
CHG2
BIT 1
DET_ST1[0]
DET_ST2[0]
DET_ST3[0]
DET_ST4[0]
IMAX_FLT1
STRT_FLT1
VDD_UVLO
WDTIME[0]
HWMODE1
DET_END1
PWR_ON1
PWR_EN1
DCD_EN1
BCKOFF1
RESET_P1
DET_EN1
Reserved
Reserved
TDISC[0]
HP_TIME
SMODE1
PE_INT
MASK0
PWEN_
REV [0]
P1_M0
CHG1
AUTO
BIT 0
AAAA,AAAA
AAAA,AAAA
AAA0,0A00
0001,0000*
0000,AAAA
0000,XXXX
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
0000,0000
1100,0000
0000,0000
0000,0000
1100,0000
0000,0000
0000,0000
0000,0000
A1A0MA
00A3A2,
RESET
STATE