adc1213s125hn/c1 NXP Semiconductors, adc1213s125hn/c1 Datasheet - Page 32

• Manufacturer Part Number: adc1213s125hn/c1
• Description: Adc1213s Series Single 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps; Serial Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 41.
Default values are highlighted.
Table 42.
Default values are highlighted.
Table 43.
Default values are highlighted.
Table 44.
Default values are highlighted.
Table 45.
Default values are highlighted.
ADC1213S_SER
Product data sheet
Bit
7 to 1
0
Bit
7
6 to 2
1 to 0
Bit
7 to 5
4 to 0
Bit
7 to 0
Bit
7
6
5 to 4
3
Symbol
-
S
Symbol
HD
-
CF[1:0]
Symbol
-
LID[4:0]
Symbol
FCHK[7:0]
Symbol
-
SCR_IN_MODE
LANE_MODE[1:0]
-
Cfg_9_S (address 0828h)
Cfg_10_HD_CF (address 0829h)
Cfg_02_2_LID (address 082Dh)
Cfg02_13_FCHK (address 084Dh)
Lane_0_Ctrl (address 0871h)
-
R/W
R
R/W
Access
R/W
Access
R/W
-
Access
-
R/W
Access
Access
-
R/W
-
All information provided in this document is subject to legal disclaimers.
Value
0000000
0
Value
*
00000
00
Value
000
11100
Value
********
Value
0
0 (reset)
1
00 (reset)
01
10
11
0
Rev. 1 — 14 March 2011
Description
not used
defines number of samples per converter per frame cycle
Description
defines high density format
not used
defines number of control words per frame clock cycle per link.
Description
not used
defines lane identification number
Description
defines the checksum value for lane
checksum corresponds to the sum of all the link configuration
parameters module 256 (as defined in JEDEC Standard
No.204A)
Description
not used
defines the input type for scrambler and 8-bit/10-bit units:
defines output type of lane output unit:
not used
(normal mode) = input of the scrambler and 8-bit/10-bit
units is the output of the frame assembly unit.
input of the scrambler and 8-bit/10-bit units is the PRBS
generator (PRBS type is defined with “PRBS_TYPE[1:0]”
(Ser_PRBS_Ctrl register)
normal mode: lane output is the 8-bit/10-bit output unit
constant mode: lane output is set to a constant (0 × 0)
toggle mode: lane output is toggling between 0 × 0 and 0 × 1
PRBS mode: lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register)
Single 12-bit ADC; serial JESD204A interface
ADC1213S series
© NXP B.V. 2011. All rights reserved.
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