adc12132 National Semiconductor Corporation, adc12132 Datasheet - Page 10

• Manufacturer Part Number: adc12132
• Description: Self-calibrating 12-bit Plus Sign Serial I/o A/d Converters With Mux And Sample/hold
• Manufacturer: National Semiconductor Corporation

www.national.com
AC Electrical Characteristics
Note 8: To guarantee accuracy, it is required that the V
pin.
Note 9: With the test condition for V
Note 10: Typical figures are at T
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figure 2 and Figure 3).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions
between −1 to 0 and 0 to +1 (see Figure 4).
Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16: Channel leakage current is measured after the channel selection.
Note 17: Timing specifications are tested at the TTL logic levels, V
to 1.4V.
Note 18: The ADC12130 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will
result in a maximum repeatability uncertainty of 0.2 LSB.
Note 19: If SCLK and CCLK are driven from the same clock source, then t
Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
J
= T
REF
A
= 25˚C and represent most likely parametric norm.
(V
REF
+ − V
REF
A
−) given as +4.096V, the 12-bit LSB is 1.0 mV. For V
+ and V
FIGURE 1. Transfer Characteristic
(Continued)
D
+ be connected together to the same power supply with separate bypass capacitors at each V
OL
= 0.4V for a falling edge and V
A
is 6, 10, 18 or 34 clock periods minimum and maximum.
10
OL
01207904
= 2.4V for a rising edge. TRI-STATE output voltage is forced
REF
= 2.5V, the 12-bit LSB is 610 µV.
01207905
+