adc12132 National Semiconductor Corporation, adc12132 Datasheet - Page 4

• Manufacturer Part Number: adc12132
• Description: Self-calibrating 12-bit Plus Sign Serial I/o A/d Converters With Mux And Sample/hold
• Manufacturer: National Semiconductor Corporation

www.national.com
Pin Descriptions
DI
DO
EOC
CS
DOR
CONV
This is the serial data input pin. The data ap-
plied to this pin is shifted at the rising edge of
SCLK into the multiplexer address and mode
select register. Table 2 through Table 4 show
the assignment of the multiplexer address and
the mode select data.
The data output pin. This pin is an active push/
pull output when CS is low. When CS is high,
this output is TRI-STATE
result (DB0–DB12) and converter status data
are clocked out at the falling edge of SCLK on
this pin. The word length and format of this
result can vary (see Table 1). The word length
and format are controlled by the data shifted
into the multiplexer address and mode select
register (see Table 4).
This pin is an active push/pull output and indi-
cates the status of the ADC12130/2/8. When
low, it signals that the A/D is busy with a con-
version, auto-calibration, auto-zero or power
down cycle. The rising edge of EOC signals the
end of one of these cycles.
This is the chip select pin. When a logic low is
applied to this pin, the rising edge of SCLK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE.
With CS low, the falling edge of SCLK shifts the
data resulting from the previous ADC conver-
sion out on DO, with the exception of the first bit
of data. When CS is low continuously, the first
bit of the data is clocked out on the rising edge
of EOC (end of conversion). When CS is
toggled, the falling edge of CS always clocks
out the first bit of data. CS should be brought
low when SCLK is low. The falling edge of CS
resets a conversion in progress and starts the
sequence for a new conversion. When CS is
brought back low during a conversion, that con-
version is prematurely terminated. The data in
the output latches may be corrupted. Therefore,
when CS is brought back low during a conver-
sion in progress the data output at that time
should be ignored. CS may also be left continu-
ously low. In this case it is imperative that the
correct number of SCLK pulses be applied to
the ADC in order to remain synchronous. After
the ADC supply power is applied it expects to
see 13 clock pulses for each I/O sequence. The
number of clock pulses the ADC expects is the
same as the digital output word length. This
word length can be modified by the data shifted
in at the DO pin. Table 4 details the data
required.
This is the data output ready pin. This pin is an
active push/pull output. It is low when the con-
version result is being shifted out and goes high
to signal that all the data has been shifted out.
A logic low is required on this pin to program
any mode or change the ADC’s configuration
as listed in the Mode Programming Table
(Continued)
®
. The A/D conversion
4
PD
CH0–CH7
COM
MUXOUT1, MUXOUT2
A/DIN1,
V
V
V
DGND
AGND
REF
REF
A
+, V
+
−
D
+
(Table 4) such as 12-bit conversion, Auto Cal,
Auto Zero etc. When this pin is high the ADC is
placed in the read data only mode. While in the
read data only mode, bringing CS low and puls-
ing SCLK will only clock out on DO any data
stored in the ADCs output shift register. The
data on DI will be neglected. A new conversion
will not be started and the ADC will remain in
the mode and/or configuration previously pro-
grammed. Read data only cannot be performed
while a conversion, Auto-Cal or Auto-Zero are
in progress.
This is the power down pin. When PD is high
the A/D is powered down; when PD is low the
A/D is powered up. The A/D takes a maximum
of 700 µs to power up after the command is
given.
These are the analog inputs of the MUX. A
channel input is selected by the address infor-
mation at the DI pin, which is loaded on the
rising edge of SCLK into the address register
(see Table 2 and Table 3).
The voltage applied to these inputs should not
exceed V
range on an unselected channel will corrupt the
reading of a selected channel.
This pin is another analog input pin. It is used
as a pseudo ground when the analog multi-
plexer is single-ended.
These
pins.
A/DIN2
These are the converter input pins. MUXOUT1
is usually tied to A/DIN1. MUXOUT2 is usually
tied to A/DIN2. If external circuitry is placed
between MUXOUT1 and A/DIN1, or MUXOUT2
and A/DIN2 it may be necessary to protect
these pins. The voltage at these pins should not
exceed V
This is the positive analog voltage reference
input. In order to maintain accuracy, the voltage
range of V
to 5.0 V
exceed V
bypassing.
The negative voltage reference input. In order
to maintain accuracy, the voltage at this pin
must not go below GND or exceed V
Figure 5).
These are the analog and digital power supply
pins. V
on the chip. These pins should be tied to the
same power supply and bypassed separately
(see Figure 5). The operating voltage range of
V
This is the digital ground pin (see Figure 5).
This is the analog ground pin (see Figure 5).
A
+ and V
A
+
DC
A
A
A
and V
REF
are
+
+ or go below GND. Exceeding this
D
+. See Figure 5 for recommended
+ is 3.0 V
or go below AGND (see Figure 6).
and the voltage at V
(V
D
REF
+
the
are not connected together
= V
DC
REF
to 5.5 V
multiplexer
+ − V
REF
DC
REF
.
−) is 1 V
+ cannot
A
+. (See
output
DC