adc1204802 National Semiconductor Corporation, adc1204802 Datasheet - Page 24

• Manufacturer Part Number: adc1204802
• Description: 12-bit Plus Sign 216khz 8-channel Sampling Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

www.national.com
Register Bit Description
b
b
ADC12048 is configured to interface with an 8-bit data bus;
data pins D
TRI-STATE. When the BW bit is a ’1’, the ADC12048 is
configured to interface with a 16-bit data bus and data pins
D
DATA REGISTER (Read Only)
This is a 13-bit read only register that holds the 12-bit +sign
conversion result in two’s compliment form. All reads per-
formed from the ADC12048 will place the contents of this
Power on State: 0000Hex
b
significant bit of the conversion result.
b
positive results and 1 for negative.
Functional Description
The ADC12048 is programmed through a digital interface
that supports an 8-bit or 16-bit data bus. The digital interface
consists of a 13-bit data input/output bus (D
control signals and two internal registers: a write only 13-bit
Configuration register and a read only 13-bit Data register.
The Configuration register programs the functionality of the
ADC12048. The 13 bits of the Configuration register are
divided into 7 fields. Each field controls a specific function of
the ADC12048: the channel selection of the MUX, the acqui-
sition time, synchronous or asynchronous conversions,
mode of operation and the data bus size.
Features and Operating Modes
SELECTABLE BUS WIDTH
The ADC12048 can be programmed to interface with an 8-bit
or 16-bit data bus. The BW bit (b
register controls the bus size. The bus width is set to 8 bits
(D
bit is cleared or 13 bits (D
set. At power-up the bus width defaults to 8 bits and any
initial programming of the ADC12048 should take this into
consideration.
In 8-bit mode the Configuration register is byte accessible.
The HB bit in the lower byte of the Configuration register is
11
0
0
0
0
1
12
11
12
13
7
: This is the Bus Width (BW) bit. When this bit is a ’0’ the
–b
: This bit contains the sign of the conversion result: 0 for
–D
–D
0
0
0
: b
are active and D
are all active. The BW bit is a ’0’ at power-up.
b
11
10
0
0
1
1
0
is the most significant bit and b
7
–D
0
b
are active and pins D
0
1
0
1
0
MSB
9
sign
b
12
12
–D
12
b
–D
Standby command. This puts the ADC in a low power consumption mode
Ful-Cal command. This will cause the ADC to perform a self-calibrating cycle that will correct
linearity and zero errors.
Auto-zero command. This will cause the ADC to perform an auto-zero cycle that corrects offset
errors.
Reset command. This puts the ADC in an idle mode.
Start command. This will put the converter in a start mode, preparing it to perform a conversion.
If in asynchronous mode (b
acquisition time has ended. In synchronous mode (b
rising edge appears on the SYNC pin.
11
8
are in TRI-STATE) if the BW
0
are active) if the BW bit is
b
12
10
) in the Configuration
b
(Continued)
9
12
12
0
–D
–D
is the least
b
8
9
0
), digital
are in
b
7
8
Conversion Data
= “0”), conversions will immediately begin after the programmed
b
24
6
register on the data bus. When reading the data register in
8-bit mode, the sign bit is extended (b
contain the sign bit).
used to access the upper byte. If the HB bit is set with a write
to the lower byte, the next byte written to the ADC will be
placed in the upper byte of the Configuration register. After
data is written to the upper byte of the Configuration register,
the HB bit will automatically be cleared, causing the next
byte written to the ADC to go to the lower byte of the
Configuration register. When reading the ADC in 8-bit mode,
the first read cycle places the lower byte of the Data register
on the data bus followed by the upper byte during the next
read cycle.
In 13-bit mode the HB bit is a don’t care condition and all bits
of the data register and Configuration register are accessible
with a single read or write cycle. Since the bus width of the
ADC12048 defaults to 8 bits after power-up, the first action
when 13-bit mode is desired must be set to the bus width to
13 bits.
WMODE
The WMODE pin is used to determine the active edge of the
write pulse. The state of this pin determines which edge of
the WR signal will cause the ADC to latch in data. This is
processor dependent. If the processor has valid data on the
bus during the falling edge of the WR signal, the WMODE
pin must be tied to V
data on the falling edge of the WR signal. If data is valid on
the rising edge of the WR signal, the WMODE pin must be
tied to DGND causing the ADC to latch in the data on the
rising edge of the WR signal.
INPUT MULTIPLEXER
The ADC12048 has an eight channel input multiplexer with a
COM input that can be used in a single-ended,
pseudo-differential or fully-differential mode. The MUX select
b
5
Command
b
4
8
b
3
= “1”), conversions will begin after a
D
b
+. This will cause the ADC to latch the
2
b
1
LSB
b
0
12
through b
8
all