adc12ds105cisq National Semiconductor Corporation, adc12ds105cisq Datasheet

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adc12ds105cisq

Manufacturer Part Number
adc12ds105cisq
Description
Dual 12-bit, 105 Msps A/d Converter With Serial Lvds Outputs
Manufacturer
National Semiconductor Corporation
Datasheet
© 2007 National Semiconductor Corporation
ADC12DS080/ADC12DS105
Dual 12-Bit, 80/105 MSPS A/D Converter with Serial LVDS
Outputs
General Description
NOTE: This is Advance Information for products current-
ly in development. ALL specifications are design targets
and are subject to change.
The ADC12DS080 and ADC12DS105 are high-performance
CMOS analog-to-digital converters capable of converting two
analog input signals into 12-bit digital words at rates up to
80/105 Mega Samples Per Second (MSPS) respectively. The
digital outputs are serialized and provided on differential
LVDS signal pairs. These converters use a differential,
pipelined architecture with digital error correction and an on-
chip sample-and-hold circuit to minimize power consumption
and the external component count, while providing excellent
dynamic performance. A unique sample-and-hold stage
yields a full-power bandwidth of 1 GHz. The AD-
C12DS080/105 may be operated from a single +3.0 or 3.3V
power supply and consumes low power. A power-down fea-
ture reduces the power consumption to very low levels while
still allowing fast wake-up time to full operation. The differen-
tial inputs accept a 2V full scale differential input swing. A
stable 1.2V internal voltage reference is provided, or the AD-
C12DS080/105 can be operated with an external 1.2V refer-
ence. Output data format (offset binary versus 2's comple-
ment) and duty cycle stabilizer are pin-selectable. The duty
cycle stabilizer maintains performance over a wide range of
clock duty cycles.
The ADC12DS080/105 is available in a 60-lead LLP package
and operates over the industrial temperature range of −40°C
to +85°C.
Connection Diagram
202117
Features
Key Specifications
Applications
1 GHz Full Power Bandwidth
Clock Duty Cycle Stabilizer
Single +3.0 or 3.3V supply operation
Serial LVDS Outputs
Serial Control Interface
Overrange outputs
60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)
For ADC12DS105
Resolution
Conversion Rate
SNR (f
SFDR (f
Full Power Bandwidth
Power Consumption
High IF Sampling Receivers
Wireless Base Station Receivers
Test and Measurement Equipment
Communications Instrumentation
Portable Instrumentation
IN
IN
= 240 MHz)
= 240 MHz)
ADVANCE INFORMATION
20211701
September 2007
67 dBFS (typ)
83 dBFS (typ)
www.national.com
1 GHz (typ)
105 MSPS
1 W (typ)
12 Bits

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adc12ds105cisq Summary of contents

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... The ADC12DS080/105 is available in a 60-lead LLP package and operates over the industrial temperature range of −40°C to +85°C. Connection Diagram © 2007 National Semiconductor Corporation Features ■ 1 GHz Full Power Bandwidth ■ Clock Duty Cycle Stabilizer ■ ...

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... Block Diagram Ordering Information Industrial (−40°C www.national.com ≤ ≤ T +85°C) A ADC12DS080CISQ ADC12DS105CISQ 2 20211702 Package 60 Pin LLP 60 Pin LLP ...

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Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I CMO 9 V ...

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Pin No. Symbol 57 PD_A 20 PD_B 27 TEST 47 WAM 48 DLC 45 OUTCLK+ 44 OUTCLK- 43 FRAME+ 42 FRAME- www.national.com Equivalent Circuit This is a two-state input controlling Power Down Power Down is enabled ...

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Pin No. Symbol Equivalent Circuit 38 SD1_A+ 37 SD1_A- 34 SD1_B+ 33 SD1_B- 36 SD0_A+ 35 SD0_A- 32 SD0_B+ 31 SD0_B- 56 SPI_EN 55 SCSb 52 SCLK 54 SDI Description Serial Data Output 1 for Channel A. This is a ...

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Pin No. Symbol 53 SDO 46 ORA 30 ORB 24 DLL_Lock ANALOG POWER 8, 16, 17, 58 12, 15, AGND Exposed Pad DIGITAL POWER 26, 40, 49 25, 39, 51 DRGND www.national.com ...

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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage on Any Pin (Not to exceed 4.2V) Input Current at ...

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ADC12DS080 Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V MHz pF/pin, . Typical values are for T CLK CM CMO L ...

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Symbol Parameter I Analog Supply Current A I Digital Output Supply Current DR Power Consumption Power Down Power Consumption ADC12DS080 Timing and AC Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V ...

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ADC12DS080 LVDS Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V MHz pF/pin. Typical values are for T CLK CM CMO L amplitude. Boldface ...

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ADC12DS105 Converter Electrical Characteristics This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifica- tions cannot be guaranteed until device characterization has taken place. Unless otherwise specified, the following specifications apply: AGND = DRGND ...

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Symbol Parameter H3 Third Harmonic Distortion SINAD Signal-to-Noise and Distortion Ratio ADC12DS105 Logic and Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V 105 MHz ...

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ADC12DS105 LVDS Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V 105 MHz pF/pin. Typical values are for T CLK CM CMO L amplitude. Boldface ...

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Note 10: Typical figures are 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not A guaranteed. Note 11: Integral Non Linearity is defined as the deviation of the ...

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Specification Definitions APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...

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Timing Diagrams FIGURE 2. Serial Output Data Format in Single-Lane Mode www.national.com Serial Output Data Timing FIGURE 1. 16 20211714 20211717 ...

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FIGURE 3. Serial Output Data Format in Dual-Lane Mode 17 20211718 www.national.com ...

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Transfer Characteristic www.national.com FIGURE 4. Transfer Characteristic 18 20211710 ...

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Functional Description Operating on a single +3.0 or 3.3V supply, the AD- C12DS080/105 digitizes two differential analog input signals to 12 bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to ensure maximum performance. ...

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Electrical Specifications section. SDI: Serial Data. Must observe setup/hold requirements with respect to the SCLK. Each cycle is 16-bits long. R/Wb: A value of '1' indicates a read ...

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Bit 2 Word Alignment Mode. This bit must be set to '0' in the single-lane mode of operation. In dual-lane mode, when this bit is set to '0' the serial data words are offset by half-word. This gives the least ...

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... Physical Dimensions TOP View...............................SIDE View...............................BOTTOM View www.national.com inches (millimeters) unless otherwise noted 60-Lead LLP Package Ordering Numbers: ADC12DS080CISQ / ADC12DS105CISQ NS Package Number SQA60A 22 ...

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Notes 23 www.national.com ...

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... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...

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