adc12ds105cisq National Semiconductor Corporation, adc12ds105cisq Datasheet - Page 21

• Manufacturer Part Number: adc12ds105cisq
• Description: Dual 12-bit, 105 Msps A/d Converter With Serial Lvds Outputs
• Manufacturer: National Semiconductor Corporation

Reset State : 08h
Bit 2
Bit 1
Bit 0
User Test Pattern Register 0, Address 1h
Word Alignment Mode.
This bit must be set to '0' in the single-lane mode
of operation.
In dual-lane mode, when this bit is set to '0' the
serial data words are offset by half-word. This
gives the least latency through the device. When
this bit is set to '1' the serial data words are in
word-aligned mode. In this mode the serial data
on the SD1 lane is additionally delayed by one
CLK cycle. (Refer to ).
Reserved. Must be set to '0'.
Reserved. Must be set to '0'.
7 6 5 4
Reserved User Test Pattern (11:8)
3
2
1
0
21
Reset State : 00h
Reset State : 00h
Bits (7:6) Reserved. Must be set to '0'.
Bits (5:0) User Test Pattern. Most-significant 6 bits of the
Bits (7:0) User Test Pattern. Least-significant 8 bits of the
User Test Pattern Register 1, Address 2h
12-bit pattern that will be sourced out of the data
outputs in Test Output Mode.
12-bit pattern that will be sourced out of the data
outputs in Test Output Mode.
User Test Pattern (7:0)
7 6 5 4 3 2 1 0
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