adc128s102wgmpr National Semiconductor Corporation, adc128s102wgmpr Datasheet
adc128s102wgmpr
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... Ordering Information NS Part Number ADC128S102WGRQV Flight Part ADC128S102WGMPR Pre-Flight Prototype ADC128S102CVAL Ceramic Evaluation Board Connection Diagram SPI ™ trademark of Motorola, Inc. © 2010 National Semiconductor Corporation ...
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Block Diagram Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I/O IN0 to IN7 DIGITAL I/O 16 SCLK 15 DOUT 14 DIN 1 CS POWER SUPPLY AGND 12 DGND ...
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Absolute Maximum Ratings Analog Supply Voltage V A Digital Supply Voltage V D Voltage on Any Pin to GND Input Current at Any Pin (Note 3) Power Dissipation (Note 4) Package Input Current (Note 3) ESD Susceptibility (Note 5) Human ...
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ADC128S102QML Converter Electrical Characteristics The following specifications apply for AGND = DGND = 0V, f unless otherwise noted. Boldface limits apply for T Symbol Parameter STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes Integral Non-Linearity (End INL Point Method) DNL ...
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Symbol Parameter Intermodulation Distortion, Second Order Terms IMD Intermodulation Distortion, Third Order Terms ANALOG INPUT CHARACTERISTICS V Input Range Leakage Current DCL C Input Capacitance INA DIGITAL INPUT CHARACTERISTICS V Input High Voltage IH V Input Low ...
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Symbol Parameter POWER SUPPLY CHARACTERISTICS (C Analog and Digital Supply Voltages Total Supply Current Normal Mode ( CS low Total Supply Current Shutdown Mode (CS high) Power Consumption Normal Mode ...
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Timing Specifications The following specifications apply for V kSPS to 1 MSPS, and C = 50pF. Boldface limits apply for T L Symbol Parameter CS Hold Time after SCLK t CSH Rising Edge CS Setup Time prior to SCLK t ...
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Burn In Delta Parameters T The following specifications apply for V kSPS to 1 MSPS, and C = 50pF Symbol Parameter INL Integral Non-LInearity Intermodulation Distortion, IMD Second Order Terms Intermodulation Distortion, IMD Third Order Terms Note 1: ...
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Timing Diagrams FIGURE 1. ADC128S102 Operational Timing Diagram FIGURE 2. ADC128S102 Serial Timing Diagram FIGURE 3. SCLK and CS Timing Parameters 9 30018106 30018150 www.national.com 30018151 ...
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Specification Definitions ACQUISITION TIME is the time required for the ADC to ac- quire the input voltage. During this time, the hold capacitor is charged by the input voltage. APERTURE DELAY is the time between the fourth falling edge of ...
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Typical Performance Characteristics unless otherwise stated. DNL INL DNL vs. Supply T = +25° MSPS SAMPLE 30018140 30018142 INL vs. Supply 30018121 MHz 40.2 kHz SCLK IN DNL 30018141 INL ...
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SNR vs. Supply ENOB vs. Supply INL vs. SCLK Duty Cycle www.national.com THD vs. Supply 30018122 DNL vs. SCLK Duty Cycle 30018133 SNR vs. SCLK Duty Cycle 30018158 12 30018132 30018155 30018161 ...
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THD vs. SCLK Duty Cycle 30018164 DNL vs. SCLK 30018156 DNL vs. SCLK 30018130 ENOB vs. SCLK Duty Cycle INL vs. SCLK INL vs. SCLK 13 30018152 30018159 30018131 www.national.com ...
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SNR vs. SCLK THD vs. SCLK ENOB vs. SCLK www.national.com SNR vs. SCLK 30018162 30018165 ENOB vs. SCLK 30018153 14 30018123 THD vs SCLK 30018124 30018145 ...
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ENOB vs. Temperature 30018154 INL vs. Temperature 30018160 THD vs. Temperature 30018166 DNL vs. Temperature SNR vs. Temperature Power Consumption vs. SCLK 15 30018157 30018163 30018144 www.national.com ...
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Functional Description The ADC128S102 is a successive-approximation analog-to- digital converter designed around a charge-redistribution dig- ital-to-analog converter. 1.1 ADC128S102 OPERATION Simplified schematics of the ADC128S102 in both track and hold operation are shown in Figure 4 tively. In Figure ...
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ADC automatically enters track mode and the falling edge seen as the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC enters track mode. While there ...
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Applications Information 2.1 TYPICAL APPLICATION CIRCUIT A typical application is shown in Figure digital supply pins are both powered in this example by the National LP2950 low-dropout voltage regulator. The analog supply is bypassed with a capacitor network located ...
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LAYOUT AND GROUNDING Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The ...
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Revision History Date Released Revision 08/21/08 A New Data Sheet, Initial Release 11/03/08 B Timing Diagrams 01/09/09 C Features, Ordering Information 06/02/09 D Features, Ordering Information, Electrical Section 10/27/09 E Operating Ratings, Electricals, Note and Typical Performance Characteristics 03/11/2010 F ...
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Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Ceramic SOIC NS Package Number WG16A 21 www.national.com ...
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... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...