adc128s102wgmpr National Semiconductor Corporation, adc128s102wgmpr Datasheet - Page 19

• Manufacturer Part Number: adc128s102wgmpr
• Description: Adc128s102qml 8-channel, 50 Ksps To 1 Msps, 12-bit A/d Converter
• Manufacturer: National Semiconductor Corporation

load capacitance form a low frequency pole, verify signal in-
tegrity once the series resistor has been added.
2.3 LAYOUT AND GROUNDING
Capacitive coupling between the noisy digital circuitry and the
sensitive analog circuitry can lead to poor performance. The
solution is to keep the analog circuitry separated from the
digital circuitry and the clock line as short as possible.
Digital circuits create substantial supply and ground current
transients. The logic noise generated could have significant
impact upon system noise performance. To avoid perfor-
mance degradation of the ADC128S102 due to supply noise,
do not use the same supply for the ADC128S102 that is used
for digital logic.
Generally, analog and digital lines should cross each other at
90° to avoid crosstalk. However, to maximize accuracy in high
resolution systems, avoid crossing analog and digital lines al-
together. It is important to keep clock lines as short as possi-
ble and isolated from ALL other lines, including other digital
lines. In addition, the clock line should also be treated as a
transmission line and be properly terminated.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected between
the converter's input pins and ground or to the reference input
pin and ground should be connected to a very clean point in
the ground plane.
We recommend the use of a single, uniform ground plane and
the use of split power planes. The power planes should be
located within the same board layer. All analog circuitry (input
amplifiers, filters, reference components, etc.) should be
placed over the analog power plane. All digital circuitry and I/
19
O lines should be placed over the digital power plane. Fur-
thermore, all components in the reference circuitry and the
input signal chain that are connected to ground should be
connected together with short traces and enter the analog
ground plane at a single, quiet point.
3.0 Radiation Environments
Careful consideration should be given to environmental con-
ditions when using a product in a radiation environment.
3.1 TOTAL IONIZING DOSE
Radiation hardness assured (RHA) products are those part
numbers with a total ionizing dose (TID) level specified in the
Ordering Information table on the front page. Testing and
qualification of these products is done on a wafer level ac-
cording to MIL-STD-883G, Test Method 1019.7. Testing is
done according to Condition A and the “Extended room tem-
perature anneal test” described in section 3.11 for application
environment dose rates less than 0.16 rad(Si)/s. Wafer level
TID data is available with lot shipments.
3.2 SINGLE EVENT LATCH-UP
One time single event latchup testing (SEL) was performed
according to EIA/JEDEC Standard, EIA/JEDEC57. Testing
was done at maximum operating temperature and supply
voltage. The linear energy transfer threshold (LETth) shown
in the Key Specifications table on the front page is the maxi-
mum LET tested. A test report is available upon request.
3.3 SINGLE EVENT UPSET
A report on single event upset (SEU) is available upon re-
quest.
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