adc1251cmj National Semiconductor Corporation, adc1251cmj Datasheet - Page 4

• Manufacturer Part Number: adc1251cmj
• Description: Self-calibrating 12-bit Plus Sign A/d Converter With Sample-and-hold
• Manufacturer: National Semiconductor Corporation

f
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
CLK
C
C
A
IA
ZA
D(EOC)L
CAL
W(CAL)L
W(WR)L
ACC
0H
PD(INT)
RR
AC Electrical Characteristics
The following specifications apply for DV
Boldface limits apply for T
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed
specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test
conditions
Note 2 All voltages are measured with respect to AGND and DGND unless otherwise specified
Note 3 When the input voltage (V
5 mA The 20 mA maximum package input current rating allows the voltage at any four pins with an input current limit of 5 mA to simultaneously exceed the power
supply voltages
Note 4 The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation
output) Caution should be taken not to exceed absolute maximum power rating when the device is operating in severe fault condition (ex when any inputs or
outputs exceed the power supply) The maximum power dissipation must be derated at elevated temperatures and is dictated by T
temperature) i
is P
resistance (i
Note 5 Human body model 100 pF discharged through a 1 5 kX resistor
t
1H
Dmax
e
Clock Frequency
Clock Duty Cycle
Conversion Time Using WR
to Start a Conversion
Conversion Time Using S H
to Start a Conversion
Acquisition Time (Note 15)
Internal Acquisition Time
(When Using WR Control Only)
Auto Zero Time
Delay from Hold Command
to Falling Edge of EOC
Calibration Time
Calibration Pulse Width
Minimum WR Pulse Width
Maximum Access Time
(Delay from Falling Edge of
RD to Output Data Valid)
TRI-STATE Control
(Delay from Rising Edge of
RD to Hi-Z State)
Maximum Delay from Falling Edge
of RD or WR to Reset of INT
Delay between Successive RD Pulses
(T
JA
Jmax
) of the ADC1251 with CMJ BIJ and CIJ suffixes when board mounted is 51 C W
JA
(package junction to ambient thermal resistance) and T
b
T
A
) i
Parameter
JA
a
or the number given in the Absolute Maximum Ratings whichever is lower For this device T
Acquisition Time
IN
A
) at any pin exceeds the power supply rails (V
e
T
J
e
T
MIN
CC
e
to T
f
f
AZ
f
R
f
Using WR Control
Using S H Control
f
(Note 16)
C
R
CLK
CLK
CLK
CLK
CLK
AV
SOURCE
L
L
MAX
e
e
e
CC
e
e
e
e
e
100 pF
1 kX C
‘‘1’’
3 5 MHz AZ
1 75 MHz AZ
3 5 MHz AZ
1 75 MHz
3 5 MHz
e a
Conditions
all other limits T
e
A
(ambient temperature) The maximum allowable power dissipation at any temperature
50X
5 0V V
L
e
4
IN k
100 pF
b
e
e
e
V
b
‘‘1’’
‘‘1’’
e b
‘‘0’’
A
or V
e
IN l
5 0V t
T
1399(1 f
27(1 f
34(1 f
33(1 f
J
7(1 f
(Note 9)
(AV
Typical
e
15 4
18 8
200
100
399
100
0 5
6 0
7 7
9 7
3 5
50
60
60
50
30
30
r
CC
25 C (Notes 6 and 7)
CLK
e
CLK
CLK
CLK
or DV
CLK
t
)
f
)
)
)
e
)
CC
27(1 f
34(1 f
33(1 f
) the current at that pin should be limited to
20 ns unless otherwise specified
1399 (1 f
Jmax
(Notes 10 19)
7(1 f
CLK
CLK
CLK
e
15 65
19 05
7 95
9 95
Limit
350
150
400
200
200
175
3 5
3 5
40
60
95
70
60
a
150 C and the typical thermal
)
)
)
CLK
1 TTL Load on each digital
a
a
a
Jmax
CLK
250 ns
250 ns
250 ns
)
(maximum junction
)
MHz(max)
MHz(min)
ms(max)
ms(max)
ms(max)
ms(max)
ms(max)
%(max)
ns(max)
ns(max)
ns(max)
ns(max)
ns(max)
ms(min)
%(min)
ns(min)
ns(min)
ns(min)
(Limit)
Units
(max)
(max)
(max)
(max)
(max)
MHz
%