adc1251cmj National Semiconductor Corporation, adc1251cmj Datasheet - Page 5

• Manufacturer Part Number: adc1251cmj
• Description: Self-calibrating 12-bit Plus Sign A/d Converter With Sample-and-hold
• Manufacturer: National Semiconductor Corporation

Electrical Characteristics
Note 6 Two on-chip diodes are tied to the analog input as shown below Errors in the A D conversion can occur if these diodes are forward biased more than
50 mV This means that if AV
Note 7 A diode exists between AV
To guarantee accuracy it is required that the AV
Note 8 Accuracy is guaranteed at f
curves
Note 9 Typicals are at T
Note 10 Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 11 Positive linearity error is defined as the deviation of the analog value expressed in LSBs from the straight line that passes through positive full scale and
zero For negative linearity error the straight line passes through negative full scale and zero (See Figures 1b and 1c )
Note 12 The ADC1251’s self-calibration technique ensures linearity full scale and offset errors as specified but noise inherent in the self-calibration process will
result in a repeatability uncertainty of
Note 13 If T
Note 14 After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes
Note 15 When using the WR control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the
end of the interval t
is synchronous to the rising edge of WR then t
Note 16 The CAL line must be high before a conversion is started
Note 17 The specifications for these parameters are valid after an Auto-Cal cycle has been completed
Note 18 The ADC1251 reference ladder is composed solely of capacitors
Note 19 A Military RETS Electrical Test Specification is available on request At time of printing the ADC1251CMJ 883 RETS specification complies fully with the
boldface limits in this column
A
changes then an Auto-Zero or Auto-Cal cycle will have to be re-started See the typical performance characteristic curves
A
therefore making t
J
e
CC
25 C and represent most likely parametric norm
and DV
CC
CLK
g
and DV
A
0 20 LSB
CC
end a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR If the falling edge of the clock
e
are minimum (4 75 V
3 5 MHz At higher or lower clock frequencies accuracy may degrade See the Typical Performance Characteristics
CC
A
CC
will end exactly 6 5 clock periods after the rising edge of WR This does not occur when S H control is used
as shown below
and DV
(Continued)
FIGURE 1a Transfer Characteristic
CC
be connected together to a power supply with separate bypass filters at each V
DC
) and V
b
is maximum (
5
b
4 75 V
DC
) the analog input full-scale voltage must be
TL H 11024 – 4
TL H 11024 – 5
CC
pin
TL H 11024 – 6
s g
4 8 V
DC