adc14071eval National Semiconductor Corporation, adc14071eval Datasheet - Page 7

• Manufacturer Part Number: adc14071eval
• Description: 14-bit, 7 Msps, 380 Mw A/d Converter
• Manufacturer: National Semiconductor Corporation

Symbol
The following specifications apply for AGND = DGND = DR GND = 0V, V
V
apply for T
AC Electrical Characteristics
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
(10 mA for pins 1, 45 and 47). The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input
current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (
TQFP,
device under normal operation will typically be about 400 mW (380 mW quiescent power +20 mW due to 1 TTL load on each digital output. The values for maximum
power dissipation listed above will be reached only when the ADC14071 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the
power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k
Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 0.3V above V
is limited per (Note 3). However, errors in the A/D conversion can occur if the input goes above (V
V
Note 8: To guarantee accuracy, it is required that V
Note 9: With the test condition for V
Note 10: Typical figures are at T
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Integral Non-Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scale and
negative full-scale.
Note 13: Optimum SNR performance will be obtained by keeping the reference input in the 1.8V to 2.7V range. The LM4041CIM3-ADJ (SOT-23 package) or the
LM4041CIZ-ADJ (TO-92 package bandgap voltage reference is recommended for this application.
t
A
REF IN
CONV
t
t
t
t
t
t
t
DIS
CH
OD
is 4.75V
CL
AD
EN
AJ
ja
= +2.0V, V
is 76˚C/W, so P
DC
, the full-scale input voltage must be
A
Conversion Clock Low Time
Conversion Clock High Time
Conversion Latency
Aperture Delay
Aperture Jitter
Rising Edge of CLOCK to Data Valid
OE Low to Data Valid on D00 – D13
OE High to D0 – D13 into TRI-STATE
= T
J
IN
= T
D
(common mode) = 1.0V, f
MAX = 1,345 mW at 25˚C and 855 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this
MIN
to T
A
= T
REF
MAX
J
JA
= 25˚C, and represent most likely parametric norms.
= (V
), and the ambient temperature (T
: all other limits T
Parameter
REF
ESD Protection Scheme for Input and Output Pins
+ − V
A
and V
2.75V
REF
J
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T
−) given as +2.0V, the 14-bit LSB is 244 µV.
CLK
DC
D
be connected together and to the same power supply with separate bypass capacitors at each V
or
(Continued)
= 7 MHz
®
A
−300 mV to ensure accurate conversions.
= T
J
= 25˚C (Notes 7, 8, 9)
A
@
), and can be calculated using the formula P
resistor. Machine model is 220 pF discharged through ZERO ohms.
50% duty cycle, t
7
IN
<
AGND or V
DRV
DRV
A
A
Conditions
or to 0.3V below GND will not damage this device, provided current
DS101101-8
= V
IN
A
−2.0V) or below GND by more than 300 mV. As an example, if
>
D
D
D
r
V
, t
= 3.0V
= 5.0V
A
= +5.0V
f
or V
= 4 ns, C
D
), the current at that pin should be limited to 25 mA
DC
(Note 10)
Typical
, DR V
L
63
63
12
45
34
35
12
= 20 pF/pin. Boldface limits
3
5
D
MAX = (T
D
= 3.0V or 5.0V, PD = 0V,
J
(Note 11)
max - T
Limits
58
53
A
)/
JA
www.national.com
. In the 48-pin
ns(max)
ns(max)
J
ps(rms)
ns(min)
ns(min)
Cycles
max, the
Units
Clock
ns
ns
ns
+
pin.