tda8026 NXP Semiconductors, tda8026 Datasheet - Page 14

• Manufacturer Part Number: tda8026
• Description: Multiple Smart Card Slot Interface Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TDA8026_1
Product data sheet
8.4.4 Device addressing
In addition, the set-up and hold times must be taken into account. The master-receiver
must signal the end of the last data byte to the slave transmitter by not sending an
acknowledge bit on the last byte that has been clocked out of the slave. The transmitter
must ensure the data line is HIGH to enable the master to generate the STOP condition.
Three device addresses are needed to control the TDA8026.
The addresses for the device are shown in
Table 5.
Bit 1 is the address bit which selects Register0 or Register1. Bit 0 defines either Read or
Write mode.
Table 6.
Bank 1 page selection is performed when the configuration byte (CSb[7:0]) is written to
the high address representing bank 0 based on the A0 pin value.
Using pin A0, two TDA8026s can be used in parallel based on the selection made to the
address selection pin A0. Pin A0 is externally hardwired to the pins V
voltage on the A0 pin sets the bit 2 address bit
Bit 7
0
A0 Pin
0
1
•
•
•
•
One high address: The high address enables selection of a bank page (Bank 0 or
Bank 1) based on a configuration byte. A bank page relates to a card slot or general
registers. See
Two low addresses: The microcontroller uses two low addresses to read and write into
the selected bank page (see
information).
When bit 0 is set to logic 1, read mode is selected
When bit 0 is set to logic 0, write mode is selected
Bank 0 base register
address (Hex)
48h
4Ch
Base addressing
Write mode addresses
Bit 6
1
All information provided in this document is subject to legal disclaimers.
Table 7
Bit 5
0
Rev. 1 — 9 March 2010
for detailed information.
Table 6 on page 14
Bit 4
0
Bank 1 Register0 address
(Hex)
40h
44h
Table 5
Bit 3
1
and
Multiple smart card slot interface IC
to
Table
Table 39 on page 37
Bit 2
A0
6.
Bank 1 Register1
address (Hex)
42h
46h
Bit 1
0
DD(INTF)
TDA8026
© NXP B.V. 2010. All rights reserved.
or GND. The
for detailed
Bit 0
R/W
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