tda8026 NXP Semiconductors, tda8026 Datasheet - Page 58

• Manufacturer Part Number: tda8026
• Description: Multiple Smart Card Slot Interface Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
21. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.4.1
8.2.4.2
8.3
8.3.1
8.3.2
8.3.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.5
8.5.1
8.5.2
8.5.2.1
8.5.2.2
8.5.3
8.5.3.1
8.5.3.2
8.5.3.3
8.5.3.4
TDA8026_1
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 8
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Clock-stop mode. . . . . . . . . . . . . . . . . . . . . . . . 9
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . 9
Entering shutdown mode . . . . . . . . . . . . . . . . . 9
Exiting shutdown mode. . . . . . . . . . . . . . . . . . 10
Voltage supervisors . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 11
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
V
external divider on PORADJ pin . . . . . . . . . . . 12
I
I
Bus conditions . . . . . . . . . . . . . . . . . . . . . . . . 13
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device addressing . . . . . . . . . . . . . . . . . . . . . 14
Banks and registers . . . . . . . . . . . . . . . . . . . . 15
Register overview . . . . . . . . . . . . . . . . . . . . . . 16
Bank 0 register description . . . . . . . . . . . . . . . 18
Bank 0 register (address: 48h) bit allocation . 18
Bank 0 bit description . . . . . . . . . . . . . . . . . . . 18
Bank 1 card slots 1 and 2 register
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bank 1 CSb[7:0] Register0 (address 40h) card
slot 1 and card slot 2 bit allocation . . . . . . . . . 18
Bank 1 Register0 card slot 1 (address 01h) and
card slot 2 (address 02h) read mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Bank 1 Register0 card slot 1 (address 01h) and
card slot 2 (address 02h) write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bank 1 CSb[7:0] Register0 (address 42h) card
slots 1 and card slot 2 bit allocation . . . . . . . . 21
2
2
DD(INTREGD)
C-bus description . . . . . . . . . . . . . . . . . . . . . 13
C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 13
voltage supervisor without
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
8.5.3.5
8.5.3.6
8.5.3.7
8.5.3.8
8.5.3.9
8.5.3.10
8.5.3.11
8.5.4
8.5.4.1
8.5.4.2
8.5.4.3
8.5.4.4
8.5.4.5
8.5.4.6
8.5.4.7
8.5.4.8
Bank 1 Register1 (REG[1:0] = 00) card slot 1
(address 01h) and card slot 2 (address 02h)
read/write mode bit descriptions . . . . . . . . . . 21
Bank 1 Register1 (REG[1:0] = 01) card slot 1
(address 01h) and card slot 2 (address 02h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bank 1 Register1 (REG[1:0] = 01) card slot 1
(address 01h) and card slot 2 (address 02h)
read/write mode bit descriptions . . . . . . . . . . 23
Bank 1 Register1 (REG[1:0] = 10) card slot 1
(address 01h) and card slot 2 (address 02h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bank 1 Register1 (REG[1:0] = 10) card slot 1
(address 01h) and card slot 2 (address 02h)
read/write mode bit descriptions . . . . . . . . . . 23
Bank 1 Register1 (REG[1:0] = 11) card slot 1
(address 01h) and card slot 2 (address 02h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bank 1 Register1 (REG[1:0] = 11) card slot 1
(address 01h) and card slot 2 (address 02h)
read/write mode bit descriptions . . . . . . . . . . 23
Card slots 3 to 5 register descriptions . . . . . . 24
Bank 1 CSb[7:0] Register0 (address 40h) card
slots 3 to 5 bit allocation. . . . . . . . . . . . . . . . . 24
Bank 1 Register0 card slot 3 (address 03h), card
slot 4 (address 04h) and card slot 5
(address 05h) read mode bit descriptions . . . 24
Bank 1 Register0 card slot 3 (address 03h), card
slot 4 (address 04h) and card slot 5
(address 05h) write mode bit descriptions . . . 25
Bank 1 CSb[7:0] Register1 (address 42h) card
slots 3 and 5 bit allocation . . . . . . . . . . . . . . . 26
Bank 1 Register1 (REG[1:0] = 00) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) read/write mode. . . . . . . 26
Bank 1 Register1 (REG[1:0] = 01) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) bit allocation . . . . . . . . . 27
Bank 1 Register1 (REG[1:0] = 01) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) read/write mode bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bank 1 Register1 (REG[1:0] = 10) card slot 3
(address 03h), card slot 4 (address 04h) and card
slot 5 (address 05h) bit allocation . . . . . . . . . 28
Multiple smart card slot interface IC
TDA8026
© NXP B.V. 2010. All rights reserved.
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