tda8295 NXP Semiconductors, tda8295 Datasheet - Page 8

• Manufacturer Part Number: tda8295
• Description: Tda8295 Digital Global Standard Low If Demodulator For Analog Tv And Fm Radio
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 4.
TDA8295_1
Product data sheet
Symbol
Reset
RST_N
Reference
XIN
XOUT
I
SDA
SCL
SADDR0
SADDR1
I
GPIO2/SDA_O
GPIO1/SCL_O
V-sync or GPIO
GPIO0/VSYNC
Tuner IF AGC
IF_AGC
2
2
C-bus
C-bus feed-through switch or GPIO
Pin description
7.2 Pin description
Pin
21
8
9
29
28
19
20
31
32
33
37
Table 3.
Pin
31
33
35
37
39
Type
I
I
O
I/O, OD
I
I
I
I/O, OD
I/O, OD
I/O, OD
I/O, OD, T tuner IF AGC output
Symbol
GPIO2/SDA_O
GPIO0/VSYNC
V
IF_AGC
V
[1][2]
SSDR
DDD(ADC)(3V3)
Pin allocation table
Digital global standard low IF demodulator for analog TV and FM radio
Description
The RST_N input is asynchronous and active LOW, and clears the TDA8295.
When RST_N goes LOW, the circuit immediately enters its Reset mode and
normal operation will resume four XIN signal falling edges later after RST_N
returns HIGH. Internal register contents are all initialized to their default values.
The minimum width of RST_N at LOW level is four XIN clock periods.
Crystal oscillator input pin. In Slave mode (typically), the XIN input simply
receives a 16 MHz clock signal from an external device (typically from the
TDA8275A or TDA1827x). In Oscillator mode, a fundamental 16 MHz (typically)
crystal is connected between pin XIN and pin XOUT.
Crystal oscillator output pin. In Slave mode, the XOUT output is not connected.
In Oscillator mode a fundamental 16 MHz (typically) crystal is connected
between pin XIN and pin XOUT.
I
requires an external pull-up resistor (typically 4.7 k ).
I
of 400 kHz. It is generated by the system I
These two bits allow to select four possible I
permits to use several TDA8295 in the same application and/or to avoid conflict
with other ICs. The complete I
SADDR0 (see also
SDA_O is equivalent to SDA but can be 3-stated by I
the output of a switch controlled by I2CSW_EN parameter. SDA_O is an
open-drain output and therefore requires an external pull-up resistor
(see
SCL_O is equivalent to SCL input but can be 3-stated by I
SCL_O is an open-drain output and therefore requires an external pull-up
resistor (see
a capacitor C = 33 pF to GND must be added (see
vertical synchronization pulse needed for the NXP Silicon Tuner
(see
2
2
C-bus bidirectional serial data. SDA is an open-drain output and therefore
C-bus clock input. SCL is nominally a square wave with a maximum frequency
Section
Section
Rev. 01 — 4 February 2008
Section
9.3.20).
9.3.20)
…continued
Section
9.3.20). For proper functioning of the I
9.1).
2
C-bus address is: 1, 0, 0, SADDR1, 0, 1,
Pin
32
34
36
38
40
Symbol
GPIO1/SCL_O
V
i.c.
i.c.
V
2
C-bus master.
DDDR(3V3)
SSA(ADC)
2
C-bus addresses, and therefore
Section
2
C-bus programming. It is
2
C-bus programming.
2
13.6).
C-bus feed-through,
TDA8295
© NXP B.V. 2008. All rights reserved.
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