pca9542a NXP Semiconductors, pca9542a Datasheet - Page 7

• Manufacturer Part Number: pca9542a
• Description: Pca9542a 2-channel I2c Multiplexer And Interrupt Logic
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
2004 Sep 29
2-channel I
BY TRANSMITTER
DATA OUTPUT
2
DATA OUTPUT
BY RECEIVER
C multiplexer and interrupt logic
SDA
SCL FROM
SDA
MASTER
start condition
start condition
S
S
START condition
1
1
S
1
1
SLAVE ADDRESS
SLAVE ADDRESS
1
1
Figure 9. Acknowledgement on the I
0
0
A2
A2
Figure 10. WRITE control register
Figure 11. READ control register
1
A1 A0
A1
A0
R/W
R/W
0
1
2
A
A
acknowledge
from slave
acknowledge
from slave
7
X
X
X
X
CONTROL REGISTER
not acknowledge
CONTROL REGISTER
INT1
X
acknowledge
INT0
X
8
2
X
X
C-bus
B2
B2
no acknowledge
from master
acknowledge
from slave
B1
B1
9
B0
B0
last byte
NA
A
P
P
stop condition
clock pulse for
acknowledgement
SW00481
SW00801
PCA9542A
Product data sheet
SW00368