pca9512dp NXP Semiconductors, pca9512dp Datasheet - Page 2

• Manufacturer Part Number: pca9512dp
• Description: Level Shifting Hot Swappable I2c And Smbus Buffer
• Manufacturer: NXP Semiconductors

DESCRIPTION
The PCA9512 is a hot swappable I
I/O card insertion into a live backplane without corruption of the data
and clock buses and includes two dedicated supply voltage pins to
provide level shifting between 3.3 V and 5 V systems while
maintaining the best noise margin for each voltage level. Either pin
may be powered with supply voltages ranging from 2.7 V to 5.5 V
with no constraints on which supply voltage is higher. Control
circuitry prevents the backplane from being connected to the card
until a stop bit or bus idle occurs on the backplane without bus
contention on the card. When the connection is made, the PCA9512
provides bi-directional buffering, keeping the backplane and card
capacitances isolated.
The dynamic offset design of the PCA9510/11/12/13/14 I/O drivers
allow them to be connected to another PCA9510/11/12/13/14 device
in series or in parallel and to the A side of the PCA9517. The
PCA9510/11/12/13/14 can not connect to the static offset I/Os used
on the PCA9515/15A/16/16A/17 B side and PCA9518.
FEATURES
APPLICATION
ORDERING INFORMATION
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
Philips Semiconductors
2004 Oct 05
Bi-directional buffer for SDA and SCL lines increases fanout and
prevents SDA and SCL corruption during live board insertion and
removal from multi-point backplane systems
Compatible with I
standards
to disable V/ t rise time accelerators through the ACC pin for
lightly loaded systems
5 V to 3.3 V level translation with optimum noise margin
High-impedance SDA, SCL pins for V
1 V precharge on all SDA and SCL lines
Supports clock stretching and multiple master
arbitration/synchronization
Operating power supply voltage range: 2.7 V to 5.5 V
5.5 V tolerant I/Os
0 kHz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
Packages offered: SO8, TSSOP8 (MSOP8)
cPCI, VME, AdvancedTCA cards and other multi-point backplane
cards that are required to be inserted or removed from an
operating system.
Level shifting hot swappable I
8-pin plastic SO
8-pin plastic TSSOP (MSOP)
V/ t rise time accelerators on all SDA and SCL lines with ability
PACKAGES
2
C standard mode, I
2
C and SMBus buffer that allows
2
CC
TEMPERATURE RANGE
C fast mode, and SMBus
or V
–40 C to +85 C
–40 C to +85 C
CC2
= 0 V
2
C and SMBus buffer
2
ORDER CODE
PCA9512DP
PIN CONFIGURATION
PIN DESCRIPTION
PCA9512D
PIN
1
2
3
4
5
6
7
8
SYMBOL
V
SCLOUT
SCLIN
GND
ACC
SDAIN
SDAOUT
V
CC2
CC
SCLOUT
SCLIN
Figure 1. Pin configuration.
V
GND
TOPSIDE MARK
CC2
DESCRIPTION
Supply voltage for devices on the card
I
SDAOUT and SCLOUT to this pin.
Serial clock output to and from the SCL bus
on the card.
Serial clock input to and from the SCL bus
on the backplane.
Ground. Connect this pin to a ground plane
for best results.
CMOS threshold digital input pin that
enables and disables the rise-time
accelerators on all four SDA and SCL pins.
ACC enables all accelerators when set to
V
Serial data input to and from the SDA bus on
the backplane/long distance bus.
Serial data output to and from the SDA bus
on the card.
Power supply. From the backplane, connect
pull-up resistors from SDAIN and SCLIN to
this pin.
2
CC2
C-buses. Connect pull-up resistors from
PCA9512
1
2
3
4
9512
, and turns them off when set to GND.
TOP VIEW
8
7
6
5
DRAWING NUMBER
V
SDAOUT
SDAIN
ACC
CC
Product data sheet
PCA9512
SOT505-1
SOT96-1
SW02070