pca9512dp NXP Semiconductors, pca9512dp Datasheet - Page 4

• Manufacturer Part Number: pca9512dp
• Description: Level Shifting Hot Swappable I2c And Smbus Buffer
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FEATURE SELECTION CHART
OPERATION
Start-up
When the PCA9512 is powered up either V
and either may be more positive or they may can be equal, however
the PCA9512 will not leave the under voltage lock out/initialization
state until both V
or V
out/initialization state. In the under voltage lock out state the
connection circuitry is disabled, the rise time accelerators are
disabled, and the precharge circuitry is also disabled. After both V
and V
enters the initialization state, during this state the 1 V precharge
circuitry is activated and pulls up the SDA and SCL pins to 1 V
through individual 100 k nominal resistors. At the end of the
initialization state the “Stop Bit And Bus Idle” detect circuit is
enabled. When all the SDA and SCL pins have been HIGH for the
bus idle time or when all pins are HIGH and a stop condition is seen
on the SDAIN and SCLIN pins, the connect circuitry is activated,
connecting SDAIN to SDAOUT and SCLIN to SCLOUT. The 1 V
precharge circuitry is disabled when the connection is made, unless
the ACC pin is LOW, the rise time accelerators are enabled at this
time also.
Connection Circuitry
Once the connection circuitry is activated, the behavior of SDAIN
and SDAOUT as well as SCLIN and SCLOUT become identical with
each acting as a bidirectional buffer that isolated the input bus
capacitance from the output bus capacitance while communicating
the logic levels. If V
performed between input and output. A LOW forced on either
SDAIN or SDAOUT will cause the other pin to be driven LOW by the
2004 Oct 05
Idle detect
High impedance SDA, SCL pins for V
Rise time accelerator circuitry on all SDA and SCL lines
Rise time accelerator circuitry hardware disable pin for lightly loaded
systems
Rise time accelerator threshold 0.8 V vs 0.6 V improves noise margin
Ready open drain output
Two V
margins
1 V precharge on all SDA and SCL lines
92 A current source on SCLIN and SDAIN for PICMG applications
Level shifting hot swappable I
CC2
CC2
CC
drops below 2.0 V it will return to the under voltage lock
are valid, independent of which is higher, the PCA9512
pins to support 5 V to 3.3 V level translation with improved noise
CC
CC
and V
V
CC2
CC2
, then a level shifting function is also
have gone above 2.5 V. If either V
FEATURES
CC
= 0 V
CC
or V
CC2
2
may rise first
C and SMBus buffer
CC
CC
4
PCA9512. The same is also true for the SCL pins. Noise between
0.7V
V
because a falling edge is only recognized when it falls below the
0.7V
SCLOUT pins) with a slew rate of at least 1.25 V/ s. When a falling
edge is seen on one pin the other pin in the pair turns on a pull down
driver that is reference to a small voltage above the falling pin. The
driver will pull the pin down at a slow rate determined by the driver
and the load. The first falling pin may have a fast or slow slew rate, if
it is faster than the pull down slew rate then the initial pull down rate
will continue until it is LOW. If the first falling pin has a slow slew rate
then the second pin will be pulled down at its initial slew rate only
until it is just above the first pin voltage then they will both continue
down at the slew rate of the first. Once both sides are LOW they will
remain LOW until all the external drivers have stopped driving
LOWs. If both sides are being driven LOW to the same or nearly the
same value by external drivers, which is the case for clock
stretching and is typically the case for acknowledge, and one side
external driver stops driving, that pin will rise and rise above the
nominal offset voltage until the internal driver catches up and pulls it
back down to the offset voltage. This bounce is worst for low
capacitances and low resistances, and may become excessive.
When the last external driver stops driving a LOW, that pin will
bounce up and settle out just above the other pin as both rise
together with a slew rate determined by the internal slew rate control
and the RC time constant. As long as the slew rate is at least 1.25
V/ s, when the pin voltage exceed 0.6 V the rise time accelerator
circuits are turned on and the pull down driver is turned off. If the
ACC pin is LOW the rise time accelerator circuits will be disabled
but the pull down driver will still turn off.
CC2
CC
CC
PCA9510
on the SDAOUT and SCLOUT pins is generally ignored
IN only
Yes
Yes
Yes
and V
for SDAIN and SCLIN (or 0.7V
—
—
—
—
—
CC
on the SDAIN and SCLIN pins and 0.7V
PCA9511
Yes
Yes
Yes
Yes
Yes
—
—
—
—
PCA9512
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
CC2
for SDAOUT and
PCA9513
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
PCA9512
Product data sheet
PCA9514
CC2
Yes
Yes
Yes
Yes
Yes
—
—
—
—
and