pca9519bs NXP Semiconductors, pca9519bs Datasheet
pca9519bs
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pca9519bs Summary of contents
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PCA9519 4-channel level translating I Rev. 02 — 13 August 2007 1. General description The PCA9519 is a 4-channel level translating I processor low voltage 2-wire serial bus to interface with standard I While retaining all the operating modes and ...
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... Packages offered: TSSOP20, HVQFN24 3. Ordering information Table 1. Ordering information Type number Topside Package mark Name PCA9519PW PCA9519 TSSOP20 PCA9519BS 9519 HVQFN24 4. Functional diagram Fig 1. Functional diagram of PCA9519 PCA9519_2 Product data sheet 4-channel level translating I Description plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic thermal enhanced very thin quad fl ...
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... B4 port (SMBus port (SMBus port (SMBus/I Rev. 02 — 13 August 2007 PCA9519 2 C-bus/SMBus repeater terminal 1 index area PCA9519BS Transparent top view Fig 3. Pin configuration for HVQFN24 [2] [2] [2] [2] [2] [2] [2] [2] 2 [2] C-bus side) ...
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... NXP Semiconductors Table 2. Symbol B1 n.c. [1] HVQFN package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors Port B is interoperable with all glitch filter. 6.1 Enable The EN pin is active HIGH and allows the user to select when the repeater is active. This can be used to isolate a badly behaved slave on power-up until after the system power-up reset. It should never change state during an I ...
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... NXP Semiconductors on port B to turn on and pull the port B pin down to ground. In order to illustrate what would be seen in a typical application, refer to Figure 4 would be observed on the B bus. This looks like a normal I On the port A bus of the PCA9519, the clock and data lines would have a positive offset ...
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... NXP Semiconductors 8. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage port B CC(B) V supply voltage port A CC(A) V voltage on an input/output pin I/O I input/output current I/O I input current I P total power dissipation tot T storage temperature ...
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... NXP Semiconductors Table 4. Static characteristics GND = +85 C; unless otherwise specified. amb Symbol Parameter Input and output of port B (B1 to B8) V HIGH-level input voltage IH V LOW-level input voltage IL V input clamping voltage IK I input leakage current LI I LOW-level input current ...
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... NXP Semiconductors 10. Dynamic characteristics Table 5. Dynamic characteristics Symbol Parameter 3.3 V CC(A) CC(B) t LOW-to-HIGH propagation delay PLH t HIGH-to-LOW propagation delay PHL t LOW to HIGH output transition time TLH t HIGH to LOW output transition time THL t LOW-to-HIGH propagation delay PLH t LOW to HIGH propagation delay 2 ...
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... NXP Semiconductors 10.1 AC waveforms input 0.5V CC(B) t PHL 70 % 0.5V 0.5V output CC( THL Fig 7. Propagation delay and transition times; port B to port A Fig 9. Propagation delay from port A’s external driver switching off to the port B LOW-to-HIGH transition; port A to port B 11. Test information Fig 10. Test circuit for open-drain outputs ...
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... NXP Semiconductors 12. Package outline TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 13. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 8. Acronym CDM CMOS CPU DUT ESD HBM I C-bus MM NMOS PCB RC SMBus ...
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... Document ID Release date PCA9519_2 20070813 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 2 nd – 2 bullet item: changed “V th – ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Enable 6.2 I C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Application design-in information . . . . . . . . . . 5 8 Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 10.1 AC waveforms Test information ...