pca9519bs NXP Semiconductors, pca9519bs Datasheet - Page 5

• Manufacturer Part Number: pca9519bs
• Description: 4-channel Level Translating I2c-bus/smbus Repeater
• Manufacturer: NXP Semiconductors

NXP Semiconductors
7. Application design-in information
PCA9519_2
Product data sheet
6.1 Enable
6.2 I
Port B is interoperable with all I
50 ns glitch filter.
The EN pin is active HIGH and allows the user to select when the repeater is active. This
can be used to isolate a badly behaved slave on power-up until after the system power-up
reset. It should never change state during an I
a bus operation will hang the bus and enabling part way through a bus cycle could
confuse the I
The enable pin should only change state when the bus and the repeater port are in an idle
state to prevent system failures.
As with the standard I
HIGH levels on the buffered bus (standard open-collector configuration of the I
The size of these pull-up resistors depends on the system. Each of the port A I/Os has an
internal pull-up current source and does not require the external pull-up resistor. The
port B is designed to work with Standard mode and Fast mode I
to SMBus devices. Standard mode I
limits the termination current to 3 mA in a generic I
devices and multiple masters are possible. Under certain conditions higher termination
currents can be used.
A typical application is shown in
I
devices can be placed on either bus.
When port B of the PCA9519 is pulled LOW by a driver on the I
hysteresis detects the falling edge when it goes below 0.3V
driver on port A to turn on, causing port A to pull down to about 0.2 V. When port A of the
PCA9519 falls, first a comparator detects the falling edge and causes the internal driver
2
2
Fig 4. Typical application
C-bus while the master is connected to a 3.3 V bus. Both buses run at 400 kHz. Master
C-bus systems
2
C-bus parts being enabled.
CPU
2
SDA
Rev. 02 — 13 August 2007
SCL
C-bus system, pull-up resistors are required to provide the logic
10 k
bus A
1.1 V
1.1 V
2
C-bus slaves, masters, and repeaters and includes the
Figure
4-channel level translating I
2
C-bus devices only specify 3 mA output drive; this
A1
A2
A8
EN
V
4. In this example, the CPU is running on a 1.1 V
CC(A)
PCA9519
2
V
C-bus operation because disabling during
CC(B)
2
B1
B2
B8
C-bus system where Standard mode
10 k
bus B
3.3 V
CC(B)
10 k
2
2
C-bus devices in addition
SDA
SCL
2
C-bus, a CMOS
and causes the internal
C-bus/SMBus repeater
MASTER
400 kHz
002aab642
PCA9519
© NXP B.V. 2007. All rights reserved.
2
C-bus).
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