adv7196a Analog Devices, Inc., adv7196a Datasheet
adv7196a
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adv7196a Summary of contents
Page 1
... HDTV format at 74.25 MHz or 74.1758 MHz. For any other high-definition standard but SMPTE 293M, ITU-R BT.1358, SMPTE274M or SMPTE296M the Async Timing Mode can be used to input data to the ADV7196A. For all standards, external horizontal, vertical, and blanking signals or EAV/SAV codes control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signals ...
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... ADV7196A FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 3.3 V SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . DYNAMIC–SPECIFICATIONS . . . . . . . . . . . . . . . . . . 4 3.3 V TIMING–SPECIFICATIONS . . . . . . . . . . . . . . . . . . 5 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 8 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 10 Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Undershoot Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Internal Test Pattern Generator . . . . . . . . . . . . . . . . . . . . 10 Y/CrCb Delay ...
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... RGB Mode (MR51 Sync on PrPb (MR52 Color Output Swap (MR53 Reserved (MR54–MR57 DAC TERMINATION AND LAYOUT CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . . 30 Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . 31 Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 31 Video Output Buffer and Optional Output Filter . . . . . . . 31 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 36 ADV7196A ...
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... ADV7196A–SPECIFICATIONS (V AA 3.3 V SPECIFICATIONS ( unless otherwise noted.) Parameter STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL OUTPUTS Output High Voltage Output Low Voltage Three State Leakage Current Three State Output Capacitance DIGITAL AND CONTROL INPUTS ...
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... Clock Cycles 29 Clock Cycles ADV7196A = 2470 , R = 300 . All specifications SET LOAD Conditions After This Period the 1st Clock Is Generated Relevant for Repeated Start Condition Progressive Scan Mode HDTV Mode Async Timing Mode and 1× Interpolation 1× Oversampling For 4:4:4 Pixel Input Format at ...
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... ADV7196A CLOCK PIXEL INPUT DATA t 11 CLOCK PIXEL INPUT DATA t 11 CLOCK PIXEL INPUT Cb0 DATA • • • • • • • • • • • • • • • ...
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... CLKCYCLES (1080I) MIN CLKCYCLES (720P) MIN t 3 SDA SCL 122 CLKCYCLES (525P) MIN B = 132 CLKCYCLES (625P) MIN B = 236 CLKCYCLES (1080I) MIN B = 300 CLKCYCLES (720P) MIN ADV7196A ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7196A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V) This input resets the on-chip timing generator and sets the ADV7196A into Default Register setting. Reset is an active low signal. TTL Address Input. This signal sets up the LSB of the MPU address. When this ...
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... MHz Operation –3.00dB In Progressive Scan mode possible to operate the three out- put DACs at 54 MHz or 27 MHz. The ADV7196A is supplied with a 27 MHz clock synced with the incoming data. If required, a second stage interpolation filter interpolates the data to 54 MHz before it is applied to the three output DACs ...
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... Logic Level “1” corresponds to a read operation while Logic Level “0” corresponds to a write opera- tion set by setting the ALSB pin of the ADV7196A to Logic Level “0” or Logic Level “1.” When ALSB is set to “0,” there is greater input bandwidth on the I speed data transfers on this bus. When ALSB is set to “ ...
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... SEQUENCE S = START BIT P = STOP BIT 2. In Write Mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7196A and the part will return to the idle condition. SDATA SCLOCK S START ADDR R/W ACK SUBADDRESS ACK Figure 12 illustrates an example of data transfer for a read sequence and the Start and Stop conditions ...
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... Figure 14 shows the various operations under the control of the Subaddress Register. “0” should always be written to SR7. Register Select (SR6–SR0) These bits are set up to point to the required starting address. SR5 SR4 SR3 SR2 ADV7196A SUBADDRESS REGISTER SR6 SR5 SR4 SR3 SR2 SR1 SR0 0 ...
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... An Asynchronous timing mode is also available using TSYNC, SYNC and DV as input control signals. These control signals have to be programmed by the user. Figure 17 shows an example of how to program the ADV7196A to accept a different high definition standard but SMPTE293M, SMPTE274M, SMPTE296M or ITU-R.BT1358 standard. Input Standard (MR04) Select between 525p progressive scan input or 625p progressive scan input ...
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... Start of Active Video –> 0 50% End of Active Video, E CLK SYNC TSYNC DV SET MR06 = 525 1 VIDEO OUTPUT HSYNC VSYNC DV HORIZONTAL SYNC 66 243 ADV7196A PROGRAMMABLE INPUT TIMING ACTIVE VIDEO ANALOG OUTPUT 1920 ...
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... MR1 BIT DESCRIPTION Pixel Data Enable (MR10) When this bit is set to “0,” the pixel data input to the ADV7196A is blanked such that a black screen is output from the DACs. When this bit is set to “1,” pixel data is accepted at the input pins and the ADV7196A outputs the standard set in “ ...
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... MR25 MR24 MR23 DISABLED PCLK ENABLED PCLK PCLK PCLK PCLK ADV7196A . NO DELAY Y OUTPUT MAX DELAY NO DELAY PrPb OUTPUTS MAX DELAY MR22 MR21 MR20 Y DELAY MR22 MR21 MR20 PCLK PCLK 0 1 ...
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... Figure 23 shows the various operations under the control of Mode Register 3. MR3 BIT DESCRIPTION HDTV Enable (MR30) When this bit is set to “1” the ADV7196A reverts to HDTV mode (refer to HDTV mode section). When set to “0” the ADV7196A is set up in Progressive Scan Mode (PS Mode) Reserved (MR31–MR32) A “ ...
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... PS mode and HDTV mode. The standard used for the values for Y and the color difference signals to obtain white, black and the saturated primary and complementary colors conforms to the ITU-R BT 601-4 standard. ADV7196A MR52 MR51 MR50 MR50 ...
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... Figure 29 shows the various operations under the control of Mode Register 6 . MR6 BIT DESCRIPTION MR67–MR60 The value 3Ehex must be written to this register before the PLL is reset (reset MR36) to guarantee correct operation of the ADV7196A. MR67 MR66 MR65 MR64 MR63 MR66 MR64 ...
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... Rounded to the nearest integer. The above will result in a gamma curve shown below, assuming a ramp signal as an input. ) γ IN ADV7196A γ γ /(240 – 16)] (240) – 16 x(n–16) the gamma correction register 4)0 5 ...
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... SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL There are three Filter modes available on the ADV7196A: one Sharpness Filter mode and two Adaptive Filter modes. SHARPNESS FILTER MODE To enhance or attenuate the Y signal in the frequency ranges shown in Figure 37, the following register settings must be used: Sharpness Filter must be enabled (MR17 = “ ...
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... This 8-bit-wide register is used to program the threshold value for large edges and has priority over Adaptive Threshold A and B. The recommended programmable threshold range is from 16–235, although any value in the range of 0–255 can be used. AFTC7 AFTC6 ADV7196A AFG35 AFG34 AFG33 AFG32 AFG31 AFG33– ...
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... ADV7196A SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES Sharpness Filter Application The sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the results shown in the figures below: Input data was generated by an external signal source Table V ...
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... Adaptive Filter Threshold C 28hex 3Fhex 64hex TEK RUN T TRIG’ 100ns CH4 CH4 100mV ALL FIELDS T 12.8222ms ADV7196A TRIG’ 100ns CH4 CH4 100mV ALL FIELDS T 12.8222ms Table VIII. Register Setting 40hex 85hex 00hex 78hex 00hex 80hex ...
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... Register 0. HEXMR0 BIT DESCRIPTION Output Standard Selection (MR00–MR01) These bits are used to select the output levels from the ADV7196A. If EIA 770.3 (MR01–00 = “00”) is selected, the output levels will be for blanking level, 700 mV for peak white (Y channel), ± 350 mV for Pr, Pb outputs and –300 mV for tri-level sync. ...
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... MR1 BIT DESCRIPTION Pixel Data Enable (MR10) When this bit is set to “0,” the pixel data input to the ADV7196A is blanked such that a black screen is output from the DACs. When this bit is set to “1,” pixel data is accepted at the input pins and the ADV7196A outputs to the standard set in “ ...
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... Figure 54 shows the various operations under the control of Mode Register 3 . MR3 BIT DESCRIPTION HDTV Enable (MR30) When this bit is set to “1” the ADV7196A reverts to HDTV mode. When set to “0” the ADV7196A reverts to Progressive Scan mode (PS mode). Reserved (MR31–MR32) A “0” must be written to these bits. ...
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... MR5 BIT DESCRIPTION Reserved (MR50) These bit is reserved for the revision code RGB Mode (MR51) When RGB mode is enabled (MR51 = “1”) the ADV7196A accepts unsigned binary RGB data at its input port. This control is also available in Async Timing Mode . Sync on PrPb (MR52) By default the color component output signals Pr not contain any horizontal sync pulses ...
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... To complement the excellent noise performance of the ADV7196A imperative that great care be given to the PC board layout. The layout should be optimized for lowest noise on the ADV7196A pin and AGND and power and ground lines. This can be achieved by shielding the SET digital inputs and providing good decoupling ...
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... DAC A ADV7196A DAC B DAC C Due to the high clock rates used, long clock lines to the ADV7196A should be avoided to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane ...
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... ADV7196A An optional analog reconstruction LPF might be required as an antialias filter if the ADV7196A is connected to a device that requires this filtering. The Eval ADV7196A/7EB evaluation board uses the ML6426 Microlinear IC, which provides buffering and low-pass filtering for progressive scan applications. The Eval ADV7196A/7EB Rev B and Rev C evaluation board uses the AD8057 as a buffer and a 6th order LPF ...
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... OUTPUT VOLTAGE 782mV 1023 714mV 64 0mV –286mV INPUT CODE PrPb-OUTPUT LEVELS FOR FULL I/P SECTIONS OUTPUT VOLTAGE 1023 350mV 0mV 64 –300mV –350mV ADV7196A OUTPUT VOLTAGE 700mV ACTIVE VIDEO 300mV 0mV –300mV OUTPUT VOLTAGE 350mV 300mV ACTIVE VIDEO 0mV –300mV –350mV OUTPUT VOLTAGE ...
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... ADV7196A SMPTE293M ANALOG WAVEFORM EAV CODE F 0 INPUT PIXELS CLOCK SAMPLE NUMBER 719 SMPTE274M ANALOG WAVEFORM EAV CODE F INPUT PIXELS F 4 CLOCK SAMPLE NUMBER 2112 ANCILLARY DATA (OPTIONAL 723 736 799 853 0HDATUM DIGITAL HORIZONTAL BLANKING 0HDATUM DIGITAL HORIZONTAL BLANKING ...
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... VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 565 566 567 568 569 570 583 ADV7196A ACTIVE VIDEO ACTIVE VIDEO DISPLAY 26 27 744 745 DISPLAY 21 22 560 DISPLAY 584 585 1123 ...
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... ADV7196A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 52-Lead Plastic Quad Flatpack (MQFP) (S-52) 0.557 (14.15) 0.094 (2.39) 0.537 (13.65) 0.084 (2.13) 0.398 (10.11) 0.390 (9.91) 0.037 (0.95) 0.026 (0.65 PIN 1 SEATING PLANE TOP VIEW (PINS DOWN) 0.012 (0.30 0.006 (0.15) 0.008 (0.20) 0.0256 0.014 (0.35) 0.006 (0.15) (0.65) 0.082 (2.09) 0.010 (0.25) BSC 0.078 (1.97) ...