adv7196a Analog Devices, Inc., adv7196a Datasheet - Page 27

• Manufacturer Part Number: adv7196a
• Description: Encoder With Three 11-bit Dacs, 10-bit Data Input, And Macrovision
• Manufacturer: Analog Devices, Inc.

MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4-SR0) = 01H)
Figure 51 shows the various operations under the control of Mode
Register 1.
MR1 BIT DESCRIPTION
Pixel Data Enable (MR10)
When this bit is set to “0,” the pixel data input to the ADV7196A
is blanked such that a black screen is output from the DACs. When
this bit is set to “1,” pixel data is accepted at the input pins and
the ADV7196A outputs to the standard set in “Output Standard
Selection” (MR01–00). This bit also must be set to “1” to enable
output pattern signals
Input Format (MR11)
It is possible to input data in 4:2:2 format or in 4:4:4
HDTV format
Test Pattern Enable (MR12)
Enables or disables the internal test pattern generator
.
.
ZERO MUST BE
ZERO MUST BE
WRITTEN TO
MR17–MR15
THESE BITS
WRITTEN TO
THIS BIT
MR17
MR07
MR07
MR06
0
1
DV POLARITY
MR16
MR06
ACTIVE HIGH
ACTIVE LOW
MR05
0
1
INPUT STANDARD
MR15
MR05
1080I
720P
.
MR14
0
1
ZERO MUST BE
WRITTEN TO
VBI OPEN
THIS BIT
MR14
MR04
MR04
DISABLED
ENABLED
MR13
0
1
TEST PATTERN
HATCH/FRAME
HATCH
FIELD/FRAME
MR13
Test Pattern Hatch/Frame (MR13)
If this bit is set to “0,” a cross-hatch test pattern is output from
the ADV7196A. The cross-hatch test pattern can be used to test
monitor convergence.
If this bit is set to “1,” a uniform colored frame/field test pattern
is output from the ADV7196A.
The color of the lines or the frame/field is by default white but
can be programmed to be any color using the Color Y, Color
Cr, Color Cb registers
VBI Open (MR14)
This bit enables or disables the facility of VBI data insertion during
the Vertical Blanking Interval.
For this purpose Lines 7–20 in 1080i and Lines 6–25 in 720p can
be used for VBI data insertion
Reserved (MR15–MR17)
A “0” must be written to these bits
MR03
MR03 MR02
0
0
1
1
MR12
0
1
INPUT CONTROL SIGNALS
TEST PATTERN
0
1
0
1
ENABLE
MR12
MR02
DISABLED
ENABLED
OUTPUT STANDARDS SELECTION
MR01 MR00
0
0
1
1
HSYNC/VSYNC/DV
EAV/SAV
TSYNC/SYNC/DV
RESERVED
MR11
0
1
INPUT FORMAT
0
1
0
1
MR11
MR01
4:4:4 YCRCB
4:2:2 YCRCB
EIA770.3
RESERVED
FULL I/P RANGE
RESERVED
.
MR10
0
1
PIXEL DATA
ENABLE
MR10
MR00
DISABLED
ENABLED
.
.
ADV7196A