adv7195 Analog Devices, Inc., adv7195 Datasheet
adv7195
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adv7195 Summary of contents
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... HDTV format at 74.25 MHz or 74.1758 MHz. For any other high-definition standard but SMPTE293M, ITU-R BT.1358, SMPTE274M or SMPTE296M the Async Timing Mode can be used to input data to the ADV7195. For all standards, exter- nal horizontal, vertical, and blanking signals or EAV/SAV codes control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signals ...
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... ADV7195 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 3.3 V SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . DYNAMIC–SPECIFICATIONS . . . . . . . . . . . . . . . . . . 4 3.3 V TIMING–SPECIFICATIONS . . . . . . . . . . . . . . . . . . 5 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 8 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 10 Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Undershoot Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Internal Test Pattern Generator . . . . . . . . . . . . . . . . . . . . 10 Y/CrCb Delay ...
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... Sync on PrPb (MR52 Color Output Swap (MR53 Reserved (MR54–MR57 DAC TERMINATION AND LAYOUT CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . . 30 Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . 31 Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 31 Video Output Buffer and Optional Output Filter . . . . . . . 31 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 36 –3– ADV7195 ...
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... ADV7195–SPECIFICATIONS (V AA 3.3 V SPECIFICATIONS unless otherwise noted, TJ Parameter STATIC PERFORMANCE Resolution (Each DAC) 1 Integral Nonlinearity 1 Differential Nonlinearity DIGITAL OUTPUTS Output Low Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance DIGITAL AND CONTROL INPUTS Input High Voltage, V ...
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... Clock Cycles For 4:4:4 Pixel Input Format at 1× Oversampling 29 Clock Cycles For 4:4:4 or 4:2:2 Pixel Input Format at ADV7195 = 2470 , R = 300 . All specifications SET LOAD Conditions After this Period the 1st Clock Is Generated Relevant for Repeated Start Condition Progressive Scan Mode HDTV Mode ASYNC Timing Mode and 1× ...
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... ADV7195 CLOCK PIXEL INPUT DATA t 11 CLOCK PIXEL INPUT DATA t 11 CLOCK PIXEL INPUT DATA Cb0 Cr0 Cb1 Cr1 Cb0 Cb1 Cb2 Cb3 Cr0 ...
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... CLK CYCLES (1080I) MIN MIN CLK CYCLES (720P 300 CLK CYCLES (720P) MIN MIN Figure 4. Input Timing Diagram Figure 5. MPU Port Timing Diagram –7– ADV7195 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7195 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Optional External Voltage Reference Input for DACs or Voltage Reference Out- put (1.235 V) This input resets the on-chip timing generator and sets the ADV7195 into Default Register setting. Reset is an active low signal. TTL Address Input. This signal sets up the LSB of the MPU address. When this ...
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... MHz in Progressive Scan Mode or 74.25 MHz or 74.1785 MHz in HDTV mode also possible to input 3 × bit RGB data in 4:4:4 format to the ADV7195 recommended to input data in 4:2:2 mode to make use of the chroma SSAFs on the ADV7195. As can be seen in Figures 6 and 7, this filter has 0 dB passband response and prevents signal com- ponents being loaded back into the frequency band ...
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... Logic Level “0” corresponds to a write operation set by setting the ALSB pin of the ADV7195 to Logic Level “0” or Logic Level “1.” When ALSB is set to “0,” there is greater input bandwidth on the I which allows high-speed data transfers on this bus. When ALSB is set to “ ...
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... SDA line is not pulled low on the ninth pulse Write Mode, the data for the invalid byte will not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7195 and the part will return to the idle condition. SDATA SCLOCK ...
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... REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7195 except the Subaddress Registers, which are write-only registers. The Subaddress Register determines which register the next read or write operation accesses. All communications with the part through the bus begin with an access to the Subaddress Register ...
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... Mode Register 0. MR0 BIT DESCRIPTION Output Standard Selection (MR00–MR01) These bits are used to select the output levels for the ADV7195. If EIA-770.2 (MR01–00 = “00”) is selected, the output levels will be for blanking level, 700 mV for peak white for the Y channel, ± ...
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... Start of Active Video –> 0 50% End of Active Video, E CLK SYNC TSYNC DV SET MR06 = 525 1 VIDEO OUTPUT HSYNC VSYNC DV HORIZONTAL SYNC 66 243 ADV7195 PROGRAMMABLE INPUT TIMING ACTIVE VIDEO ANALOG OUTPUT 1920 ...
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... Mode Register 1. MR1 BIT DESCRIPTION Pixel Data Enable (MR10) When this bit is set to “0,” the pixel data input to the ADV7195 is blanked such that a black screen is output from the DACs. When this bit is set to “1,” pixel data is accepted at the input pins and the ADV7195 outputs the standard set in “ ...
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... MR24 MR23 DISABLE PCLK ENABLE PCLK PCLK PCLK PCLK ADV7195 NO DELAY Y OUTPUT MAX DELAY NO DELAY PrPb OUTPUT MAX DELAY MR22 MR21 MR20 Y DELAY MR22 MR21 MR20 PCLK PCLK 0 1 ...
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... Figure 23 shows the various operations under the control of Mode Register 3. MR3 BIT DESCRIPTION HDTV Enable (MR30) When this bit is set to “1,” the ADV7195 reverts to HDTV mode (refer to HDTV mode section). When set to “0” the ADV7195 is set up in Progressive Scan Mode (PS Mode). Reserved (MR31–MR32) A “ ...
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... PS mode and HDTV mode. The standard used for the values for Y and the color difference signals to obtain white, black and the saturated primary and complementary colors conforms to the ITU-R BT 601-4 standard. ADV7195 MR51 MR50 RGB MODE MR51 ...
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... Figure 29 shows the various operations under the control of Mode Register 6. MR6 BIT DESCRIPTION MR67–MR60 The value 3EHex must be written to this register before the PLL is reset (reset MR36) to guarantee correct operation of the ADV7195. MR67 MR66 MR65 MR64 MR63 ...
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... The above will result in a gamma curve shown on the next page, assuming a ramp signal as an input. 300 250 200 150 100 γ ADV7195 γ γ /(240 – 16)] × (240–16 (n–16) into the gamma correction register. 0.5 × 0.5 × ...
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... The gamma curves shown in Figure 36 are examples only, any user-defined curve is acceptable in the range of 16–240. SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL Three Filter modes are available on the ADV7195: one Sharpness Filter mode and two Adaptive Filter modes. SHARPNESS FILTER MODE To enhance or attenuate the Y signal in the frequency ranges shown in Figure 37, the following register settings must be used: Sharpness Filter must be enabled (MR17 = “ ...
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... This 8-bit-wide register is used to program the threshold value for large edges and has priority over Adaptive Threshold A and B. The recommended programmable threshold range is from 16–235, although any value in the range of 0–255 can be used. AFTC7 AFTC6 ADV7195 AFG35 AFG34 AFG33 AFG32 AFG31 AFG33– ...
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... ADV7195 SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES Sharpness Filter Application The sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the results shown in Figure 44a and Figure 44b. Input data was generated by an external signal source. ...
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... Adaptive Filter Threshold B 3Fhex 27hex Adaptive Filter Threshold C 64hex TEK RUN T TRIG’ 100ns CH4 CH4 100mV ALL FIELDS T 12.8222ms ADV7195 T TRIG’ 100ns CH4 CH4 100mV ALL FIELDS T 12.8222ms Table VIII. Register Setting 40hex 85hex 00hex 78hex 00hex ...
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... Mode Register 0. MR0 BIT DESCRIPTION Output Standard Selection (MR00-MR01) These bits are used to select the output levels from the ADV7195. If EIA-770.3 (MR01–00 = “00”) is selected, the output levels will be for blanking level, 700 mV for peak white (Y channel), ± 350 mV for Pr, Pb outputs and –300 mV for tri-level sync. ...
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... Mode Register 1. MR1 BIT DESCRIPTION Pixel Data Enable (MR10) When this bit is set to “0,” the pixel data input to the ADV7195 is blanked such that a black screen is output from the DACs. When this bit is set to “1,” pixel data is accepted at the input pins and the ADV7195 outputs to the standard set in “ ...
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... Figure 54 shows the various operations under the control of Mode Register 3. MR3 BIT DESCRIPTION HDTV Enable (MR30) When this bit is set to “1,” the ADV7195 reverts to HDTV mode. When set to “0” the ADV7195 reverts to Progressive Scan Mode (PS mode). Reserved (MR31–MR32) A “ ...
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... MR5 BIT DESCRIPTION Reserved (MR50) This bit is reserved for the revision code. RGB Mode (MR51) When RGB mode is enabled (MR51 = “1”), the ADV7195 accepts unsigned binary RGB data at its input port. This control is also available in Async Timing Mode. Sync on PrPb (MR52) By default the color component output signals Pr not con- tain any horizontal sync pulses ...
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... To complement the REF excellent noise performance of the ADV7195 imperative that great care be given to the PC board layout. The layout should be optimized for lowest noise on the ADV7195 pin and AGND power and ground lines. This can be achieved by shielding the SET digital inputs and providing good decoupling ...
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... DAC A ADV7195 DAC B DAC C Due to the high clock rates used, long clock lines to the ADV7195 should be avoided to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane. ...
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... ADV7195 An optional analog reconstruction LPF might be required as an antialias filter if the ADV7195 is connected to a device that requires this filtering. The Eval ADV7195/ADV7196/ADV7197 EB evaluation board uses the ML6426 Microlinear IC, which provides buffering and low-pass filtering for HDTV applications. The Eval ADV7195/ADV7196/ADV7197 EB Rev. B and Rev. C evaluation board uses the AD8057 as a buffer and a sixth order filter as a LPF ...
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... OUTPUT VOLTAGE INPUT CODE 782mV 714mV ACTIVE VIDEO 0mV –286mV OUTPUT VOLTAGE 350mV ACTIVE VIDEO 0mV –300mV –350mV ADV7195 EIA-770.3, STANDARD FOR Y OUTPUT VOLTAGE 700mV 940 ACTIVE VIDEO 300mV 64 0mV –300mV EIA-770.3, STANDARD FOR Pr/Pb OUTPUT VOLTAGE 960 350mV 300mV ...
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... ADV7195 SMPTE293M ANALOG WAVEFORM F INPUT PIXELS F SAMPLE 719 NUMBER FVH = FVH AND PARITY BITS SAV = LINE 43–525 = 200H SAV = LINE 1–42 = 2AC EAV = LINE 43–525 = 274H EAV = LINE 1–42 = 2D8 SMPTE274M ANALOG WAVEFORM INPUT PIXELS SAMPLE NUMBER FVH = FVH AND PARITY BITS SAV/EAV = LINE 1– ...
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... VERTICAL BLANK VERTICAL BLANK 566 567 568 569 570 583 584 ADV7195 ACTIVE VIDEO 43 44 ACTIVE VIDEO DISPLAY 27 744 745 DISPLAY 22 560 DISPLAY 585 1123 ...
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... ADV7195 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 52-Lead Plastic Quad Flatpack (S-52) 0.557 (14.15) 0.094 (2.39) 0.537 (13.65) 0.084 (2.13) 0.398 (10.11) 0.390 (9.91) 0.037 (0.95) 0.026 (0.65 PIN 1 SEATING PLANE TOP VIEW (PINS DOWN) 0.012 (0.30 0.006 (0.15) 0.008 (0.20) 0.0256 0.014 (0.35) 0.006 (0.15) (0.65) 0.082 (2.09) 0.010 (0.25) BSC 0.078 (1.97) ...