adv7195 Analog Devices, Inc., adv7195 Datasheet - Page 13

• Manufacturer Part Number: adv7195
• Description: Encoder With Three 11-bit Dacs And 10-bit Data Input
• Manufacturer: Analog Devices, Inc.

REGISTER ACCESSES
The MPU can write to or read from all of the registers of the
ADV7195 except the Subaddress Registers, which are write-only
registers. The Subaddress Register determines which register the
next read or write operation accesses.
All communications with the part through the bus begin with an
access to the Subaddress Register. A read/write operation is
performed from/to the target address which then increments to
the next address until a Stop command on the bus is performed.
REGISTER PROGRAMMING
The following section describes the functionality of each regis-
ter. All registers can be read from as well as written to unless
otherwise stated.
ZERO SHOULD
BE WRITTEN
HERE
SR7
SR7
ZERO SHOULD
BE WRITTEN
HERE
SR7
SR7
SR6
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
SR6
SR5
SR6 SR5 SR4
ADDRESS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00h
01h
02h
03h
04h
05h
06h
07h
08h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SR5
SR4
SR6 SR5 SR4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SR3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
ADV7195 SUBADDRESS REGISTER
0
0
0
0
0
0
0
0
0
ADV7195 SUBADDRESS REGISTER
SR4
SR2
SR3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
SR1
SR3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Subaddress Register (SR7–SR0)
The Communications Register is an 8-bit write-only register.
After the part has been accessed over the bus and a read/
write operation is selected, the subaddress is set up. The Sub-
address Register determines to/from which register the
operation takes place.
Figure 14 shows the various operations under the control of the
Subaddress Register. “0” should always be written to SR7.
Register Select (SR6–SR0)
These bits are set up to point to the required starting address.
0
0
0
0
0
0
0
0
1
SR3
SR0
SR2
SR2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
SR1
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 2
MODE REGISTER 3
MODE REGISTER 4
MODE REGISTER 5
COLOR Y
COLOR CR
COLOR CB
MODE REGISTER 6
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
FILTER GAIN
CGMS DATA REGISTER 0
CGMS DATA REGISTER 1
CGMS DATA REGISTER 2
GAMMA CORRECTION REGISTER 0
GAMMA CORRECTION REGISTER 1
GAMMA CORRECTION REGISTER 2
GAMMA CORRECTION REGISTER 3
GAMMA CORRECTION REGISTER 4
GAMMA CORRECTION REGISTER 5
GAMMA CORRECTION REGISTER 6
GAMMA CORRECTION REGISTER 7
GAMMA CORRECTION REGISTER 8
GAMMA CORRECTION REGISTER 9
GAMMA CORRECTION REGISTER 10
GAMMA CORRECTION REGISTER 11
GAMMA CORRECTION REGISTER 12
GAMMA CORRECTION REGISTER 13
ADAPTIVE FILTER GAIN 1
ADAPTIVE FILTER GAIN 2
ADAPTIVE FILTER GAIN 3
ADAPTIVE FILTER THRESHOLD A
ADAPTIVE FILTER THRESHOLD B
ADAPTIVE FILTER THRESHOLD C
0
0
1
1
0
0
1
1
0
SR2
SR0
SR1
0
1
0
1
0
1
0
1
0
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 2
MODE REGISTER 3
MODE REGISTER 4
MODE REGISTER 5
COLOR Y
COLOR CR
COLOR CB
SR1
SR0
SR0
ADV7195