adv7162 Analog Devices, Inc., adv7162 Datasheet
adv7162
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adv7162 Summary of contents
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... The ADV7160/ADV7162® 96-bit pixel port Video RAM- DAC with color enhanced triple 10-bit DACs. The device also includes a PLL and 64 64 hardware cursor. The ADV7160/ ADV7162 is specifically designed for use in the graphics sub- system of high performance, color graphics workstations and windows accelerators. ...
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... Sync Enabled OUT V = 1.235 V for Specified Performance REF For 220 MHz Operation (ADV7160) For 170 MHz Operation (ADV7160) For 140 MHz Operation (ADV7160) For 220 MHz Operation (ADV7162) For 170 MHz Operation (ADV7162) For 140 MHz Operation (ADV7162) COMP = 0.1 F REV. 0 ...
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... ADV7160/ADV7162 = 37 pF). All L L Conditions/Comments Pixel CLOCK Rate Pixel CLOCK Cycle Time Pixel CLOCK High Time Pixel CLOCK Low Time Pixel CLOCK to LOADOUT Delay LOADIN Clocking Rate LOADIN Cycle Time LOADIN High Time ...
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... ADV7160/ADV7162 8,9 MPU P ORT Parameter 220 MHz 170 MHz Version Version NOTES General Notes 1 TTL input values are volts, with input rise/fall times ECL inputs (CLOCK, CLOCK) are V – ...
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... MHz max 15 ns min 15 ns min 15 ns max 15 ns max 15 ns max 15 ns max 0 ns min 20 ns min 5 ns min 15 ns max Figure 2. JTAG Timing –5– ADV7160/ADV7162 = 37 =10 pF Conditions/Comments 1 ...
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... ADV7160/ADV7162 Timing Waveforms CLOCK CLOCK t 4 LOADOUT (2:1 MULTIPLEXING) LOADOUT (4:1 MULTIPLEXING) LOADOUT (8:1 MULTIPLEXING) Figure 3. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK ) LOADIN PIXEL INPUT VALID DATA DATA VALID DATA Figure 4. LOADIN vs. Pixel Input Data –6– ...
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... DATA ANALOG OUTPUT DATA (IOR, IOG, IOB, A ... H N–1 N–1 SYNCOUT Figure 6. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (8:1 Multiplex Mode) REV ... A ... N+2 H N+2 A ... H A ... N+1 N ... A ... N+1 N N+1 N+2 A ... H A ... N+1 N+1 –7– ADV7160/ADV7162 A ... H N+2 N+2 A ... H N+2 N+2 ...
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... ADV7160/ADV7162 CLOCK LOADOUT LOADIN PIXEL A ... A N N+1 INPUT N+1 DATA ANALOG OUTPUT DATA (IOR, IOG, IOB, SYNCOUT Figure 7. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (4:1 Multiplex Mode) CLOCK LOADOUT LOADIN PIXEL A ... N INPUT D N DATA ANALOG OUTPUT DATA ...
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... IOG, IOB, SYNCOUT) Figure 10. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (2:1 Multiplex Mode) REV ... A ... N N–1 N– ... A ... N+1 N N+1 N N–1 N– –9– ADV7160/ADV7162 N N+1 N+1 N N+1 N+1 N+2 N+2 N ...
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... ADV7160/ADV7162 CLOCK PRGCKOUT (CLOCK/4) PRGCKOUT (CLOCK/8) PRGCKOUT (CLOCK/16) PRGCKOUT (CLOCK/32 Figure 11. Pixel Clock Input vs. Programmable Clock Output (PRGCKOUT SCKIN BLANK SCKOUT Figure 12. Video Data Shift Clock Input (SCKIN) & BLANK vs. Video Data Shift Clock Output (SCKOUT) CLOCK IOR ANALOG ...
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... ADV7160 is packaged in a 160-pin plastic power quad flatpack, QFP with heatsink embedded. 4 ADV7162 is packaged in a standard 160-pin plastic quad flatpack, QFP. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. ...
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... PS0 PS0 PS0 PS0 PS1 PS1 PS1 PS1 CLOCK 80 ADV7160/ADV7162 PIN ASSIGNMENTS Mnemonic Pin No. Mnemonic CLOCK 81 D9 SCKIN 82 D8 SCKOUT PRGCKOUT 85 D5 GND 86 D4 LOADOUT 87 D3 LOADIN ...
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... Color Matrix and Color Palette or bypass the Matrix and Palette. PS0 acts as an overlay input. (This mode is not available for the ADV7162.) Palette Select Mode is used to multiplex the RGB outputs of a number of devices. When the palette mode inputs match the PS bits in the mode register, the part operates as normal ...
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... ODD/EVEN Odd/Even Control (TTL Compatible Input). This input indicates which field of the frame is being displayed required to ensure proper operation of the ADV7160/ADV7162 cursor when inter- laced display mode is selected ignored when noninterlaced display mode is selected. This input should change only during the vertical blank period assumed that an odd field will always follow an even field and vice versa. Chip Enable (TTL Compatible Input). This input must be at Logic “ ...
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... The PLL can be pro- grammed to produce a pixel clock that is a multiple of the PLL reference clock. The ADV7162 is packaged in a standard plastic 160-pin quad flatpack (QFP). The ADV7160 is packaged in a plastic 160-pin power quad flatpack (PQUAD). Superior thermal distribution is achieved by the inclusion of a copper heatslug, within the standard package outline, to which the die is attached ...
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... PS0 This mode is not available if using the ADV7162. Overlay Color Mode In this mode, the PS inputs provide control for a three color overlay. Whenever the value other than “00” is placed on the overlay inputs, the corresponding overlay color is displayed. When the overlay inputs contain “00” the color is specified by the main pixel inputs ...
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... LOADOUT CLOCK The LOADOUT signal is used to directly drive the LOADIN pixel latch signal of the ADV7160/ADV7162. This is most sim- ply achieved by tying the LOADOUT and LOADIN pins to- gether. Alternatively, the LOADOUT signal can be used to drive the frame buffer’s shift clock signals, returning to the LOADIN input delayed with respect to LOADOUT ...
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... The SCKOUT signal is essentially the video memory shift con- trol signal stopped during the screen retrace. Figure 19 shows a suggested frame buffer to ADV7160/ADV7162 interface. This is a minimum chip solution and allows the ADV7160/ADV7162 con- trol the overall graphics system clocking and synchronization. ...
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... COLOR VIDEO MODES The ADV7160/ADV7162 supports a number of color video modes all at the maximum video rate. Command bits CR27–CR24 of Command Register 2 along with bit MR11 of Mode Register 1 determine the color mode. Seven color modes use the Color Palette, and three of them bypass the palette and control the DACs directly ...
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... ADV7160/ADV7162 ...
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... When 8:1 Multiplexing Mode is selected by setting Bit CR37 of B5 IOB 0 Command Register 3 to Logic “1” and bit CR36 of Command BLUE 0 Register 3 to Logic “0,” the ADV7160/ADV7162 goes into 8- DAC 0 Bit Pseudo-Color Mode irrespective of the Color Mode selected 0 by Bits CR27 to CR24 in Command Register 2. Hence 0 ...
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... Register Mapping The ADV7160/ADV7162 contains a number of on-board regis- ters including the Mode Register (MR17–MR10), Address Reg- ister (A10–A0) and many Control Registers as well as Color Palette Registers. These registers control the entire operation of the part. Figure 34 shows the internal register configuration. ...
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... ADDRESS REGISTER COLOR PALETTE (A10–A0) 7FFH – 104H RESERVED 103H – 101H OVERLAY COLOR 1– 30) 100H RESERVED 0FFH – 000H LOOK-UP TABLE RAM (256 x 30) –23– ADV7160/ADV7162 GREEN BLUE REGISTER REGISTER (G9-G0) (B9-B0) ADDRESS REG = ADDRESS REG +1 ...
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... PRGCKOUT = CLOCK/32 LOADOUT = CLOCK/4: The power-on reset is activated when V This reset is active for 1 s. The ADV7160/ADV7162 should not be accessed during this reset period. The pixel clock should be applied at power-up. Color Palette Accesses The Color Palette consists of 256 RAM locations, each location containing 30 bits of color information ...
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... Register Accesses The MPU can write to or read from all of the ADV7160/ ADV7162’s registers. C0 and C1 determine whether the Mode Register or Address Register is being accessed. Access to these Write Operation Palette Databus Read Operation ...
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... ADV7160/ADV7162 REGISTER PROGRAMMING The following section describes each register, including Address Register, Mode Register and each of the Control Registers in terms of its configuration. Address Register (A10–A0) As illustrated in the previous tables, the C1 and C0 control in- puts, in conjunction with this address register specify which control register, or color palette location is accessed by the MPU port ...
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... Reg (A10–A0) = 003H) This is an 8-bit wide “Identification” read-only register. For the ADV7160 it will always return the hexadecimal value 76H. For the ADV7162 it will always return the hexadecimal value 79H. Pixel Mask Register (Address Reg (A10–A0) = 004H) ...
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... ADV7160/ADV7162 CR29 CR28 RESERVED* TRUE COLOR/PSEUDO COLOR MODE CONTROL CR27 CR26 CR25 CR24 THESE BITS ARE READ-ONLY RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "00." ...
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... ENABLE 1 0 4311 1 1 5592 1 DISABLE SYNC RECOGNITION CONTROL (BLUE) CR42 SIGNATURE CLOCK CONTROL 0 1 CR45 0 DISABLE CLOCK 1 ENABLE CLOCK –29– ADV7160/ADV7162 CR32 CR37 CR36 ) PD BLANK PIPELINE DELAY LOADOUT LOADOUT LOADOUT PD PRGCKOUT FREQUENCY ...
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... ADV7160/ADV7162 Signature Reset Control (CR46) Taking CR46 low then high resets the signature analyzer. This is done to give a known starting point before acquiring a signature. Signature Acquire Control (CR47) This bit should be set to Logic “1” for normal operation. See “Test Diagnostic” section for more information. ...
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... Bit in the PLL Control Register, controls the feedback divider of the on-board PLL Cursor The ADV7160/ADV7162 has cursor generator on board. Several of the control registers control the cursor. These will be described in detail. The Cursor-X and Cursor-Y registers specify the position the cursor placed on the screen ...
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... CR43 and CR44 of Command Register 4. Figure 47 illustrates the resulting video waveform and the Video Output Truth Table illustrates the corresponding control input stimuli. On the ADV7160/ADV7162 SYNC can be encoded on any of the analog signals, however in practice, SYNC is generally encoded on either the IOG output or on all of the video outputs ...
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... SYNC LEVEL 0 Variations on RS-343A Various other video output configurations can be implemented by the ADV7160/ADV7162, including RS-170. The table shows calculated values of DAC Gain for some of the most common variants on the RS-343A standard. The associated waveforms are shown in the diagrams. Gain Video Signal 4224 RS343A, SYNC decoded on output ...
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... AA 0.1 F decoupling capacitor to GND. These capacitors should be placed as close as possible to the device important to note that while the ADV7160/ADV7162 con- tains circuitry to reject power supply noise, this rejection de- creases with frequency high frequency switching power supply is used, the designer should pay close attention to reduc- ing power supply noise and consider using a three terminal volt- age regulator for supplying power to the analog power plane ...
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... ANALOG POWER PLANE + 0.1µF (1% METAL) AD589 (1.2V REF) R SET COAXIAL CABLE 280 ( CONNECTORS Recommended Analog Circuit Layout –35– ADV7160/ADV7162 GROUP) AA 0.1µF 0.01µF 0.1µF 0.01µF L1 (FERRITE BEAD 0.1µF 33µF MONITOR (CRT BNC ...
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... TYPICAL FRAME BUFFER INTERFACE PLL PLL REF CLOCK ECL TO TTL CLOCK PRGCKOUT LOADOUT SCKOUT BLANK SYNC / TRISYNC SCKIN LOADIN MULTIPLEXER –36– DIVIDE BY M DIVIDE LATCH ENABLE ADV7160/ ADV7162 24 TO PALETTE/RAM & DAC REV. 0 ...
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... On the other hand, when quantized to 10 bits via the 10-bit RAMs and 10-bit DACs of the ADV7160/ ADV7162, all changes on the input 8-bit data are reflected in corresponding changes in the 10-bit data. The graph shows a typical gamma curve corresponding to a gamma value of 2 ...
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... Write (xxxxxxxx)* to PLLCommand Register Write (xx0xxxxx)* to Mode Register (MR1) Write (xx1xxxxx)* to Mode Register (MR1) Write (xx0xxxxx)* to Mode Register (MR1) *x represents either value that the bit should be set to, depending on the desired operating mode of the ADV7160/ADV7162. APPENDIX 4 INITIALIZATION AND PROGRAMMING C1 C0 R/W Comment ...
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... Write FFH (blue data) to RAM location (FFH) **These command lines reset the ADV7162. The pipelines for each of the Red, Green & Blue pixel inputs are synchronously reset to the Multiplexer's “A” input. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” ...
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... The ADV7160/ADV7162 contains onboard circuitry that enables both device and system level test diagnostics. The ADV7160/ ADV7162 has a signature analyzer in the pixel datapath, just before the DAC decoders. The signature analyzer consists of a 33-bit linear feedback shift register. The 30-bit pixel value is fed as a parallel input into the analyzer ...
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... JTAG Test Port JTAG Test Port is a 4-pin interface consisting of: TCK: Test Clock TMS: Test Mode Select TDI: Test Data Input TDO: Test Data Output To put the ADV7160/ADV7162 into the required mode, the In- struction Register must be loaded. INSTRUCTION INSTRUCTION REGISTER CODE EXTEST SAMPLE/PRELOAD ...
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... Power Dissipation The diagrams show graphs of power dissipation in watts versus pixel clock frequency for the ADV7160 and ADV7162. When using the ADV7162 in Bypass Mode, the Pixel Mask Register should be programmed to 00H to reduce power further. 2.25 V ...
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... PAGE INDEX Topic FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 1 & 15 ADV7160/ADV7162 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 ADV7160/ADV7162 SPECIFICATIONS . . . . . . . . . . . . . . . . . 2 ADV7160/ADV7162 TIMING CHARACTERISTICS . . . . . 3-5 TIMING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . 11 PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . 13-14 CIRCUIT DETAILS AND OPERATION . . . . . . . . . . . . . . . . 15 PIXEL PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 CLOCK CONTROL CIRCUIT ...
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... ADV7160/ADV7162 0.037 (0.95) 0.026 (0.65) SEATING 0.004 (0.10) 0.070 (1.77) 0.062 (1.57) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). S-160 160-Lead Plastic Quad Flatpack 1.239 (31.45) 1.219 (30.95) 0.160 (4.07) MAX 1.107 (28.10) 1.100 (27.90 120 121 4 4 MAX TOP VIEW (PINS DOWN) PLANE PIN 1 10 160 1 MAX 0.070 (1.77) 0.062 (1.57) 0.026 (0.65) MIN ...