adv7162 Analog Devices, Inc., adv7162 Datasheet - Page 29

• Manufacturer Part Number: adv7162
• Description: 96-bit, 220 Mhz True-color Video Ram-dac
• Manufacturer: Analog Devices, Inc.

REV. 0
COMMAND REGISTER 4 (CR4)
(ADDRESS REG (A10–A0) = 008H)
This register contains a number of control bits as shown in the
diagram. CR4 is a 10-bit wide register. However for program-
ming purposes, it may be considered as an 8-bit wide register
(CR49 and CR48 are both reserved).
Figure 43 shows the various operations under the control of
CR4. This register can be read from as well written to. In read
mode, CR49 and CR48 are both returned as zeros.
COMMAND REGISTER 4-BIT DESCRIPTION
HDTV SYNC Enable (CR40)
This bit specifies whether the video TRISYNC Input is to be
encoded, enabling the DAC outputs to generate a Tri-Level
Sync.
*
THESE BITS ARE READ-ONLY
RESERVED BITS.
A READ CYCLE WILL RETURN
ZEROS "00."
*
THESE BITS ARE READ-ONLY
RESERVED BITS.
A READ CYCLE WILL RETURN
ZEROS "00."
CR37 CR36
CR39
CR49
RESERVED*
0
0
1
1
RESERVED*
Reserved*
SIGNATURE ACQUIRE
CR47
0
1
0
1
0
1
CR38
1:1 MUXING: LOADOUT = CLOCK
2:1 MUXING: LOADOUT = CLOCK
8:1 MUXING: LOADOUT = CLOCK
4:1 MUXING: LOADOUT = CLOCK
CR48
DISABLE
ENABLE
Figure 43. Command Register 4 (CR4) (CRF49–CR40)
Figure 42. Command Register 3 (CR3) (CR39–CR30)
Pixel Multiplex Control
CR37
CR47
CR46
SIGNATURE RESET
0
1
CR45
ENABLE
DISABLE
0
1
SIGNATURE CLOCK
CR36
CR46
BE WRITTEN TO
ZERO SHOULD
CONTROL
THIS BIT
DISABLE CLOCK
ENABLE CLOCK
CR35
(0)
CR35
CR45
1
2
8 (PSEUDO COLOR ONLY)
4
–29–
CR44 CR43
0
0
1
1
SYNC Recognition Control on Red (CR41)
This bit specifies whether the video SYNC Input is to be en-
coded onto the IOR analog output or ignored.
SYNC Recognition Control on Blue (CR42)
This bit specifies whether the video SYNC Input is to be en-
coded onto the IOB analog output or ignored.
Gain Control (CR44–CR43)
These bits specifies the amount of gain on the DAC depending
on the standard required. See “DAC and Video Outputs” sec-
tion for more detail. For gain settings that have no pedestal, the
pedestal is automatically disabled independently of CR23.
Signature Clock Control (CR45)
This bit enables or disables the clock to the signature analyzer.
CR34 CR33 CR32
DAC GAIN
EXTRA BLANK PIPELINE DELAY CONTROL
CR34
CR44
(ADDS TO PIXEL PIPELINE DELAY; t
0
0
0
1
0
1
0
1
CR42
SYNC RECOGNITION
.........
.........
CONTROL (BLUE)
0
1
0
0
1
1
3996
4224
4311
5592
CR33
CR43
IGNORE
DECODE
0
1
0
1
BLANK PIPELINE DELAY
t
t
t
t
PD
PD
PD
PD
CR32
+ 1 x LOADOUT
+ 2 x LOADOUT
+ 7 x LOADOUT
SYNC RECOGNITION
CR41
CR42
0
1
CONTROL (RED)
CR31 CR30
PRGCKOUT FREQUENCY
0
0
1
1
CR40
IGNORE
DECODE
HDTV SYNC CONTROL
0
1
ADV7160/ADV7162
CR37
CONTROL
0
1
0
1
CR41
PD
DISABLE TRI-SYNC
ENABLE TRI-SYNC
CLOCK
CLOCK
CLOCK
CLOCK
)
CR36
CR40
4
8
16
32