adv7305a Analog Devices, Inc., adv7305a Datasheet
adv7305a
Available stocks
Related parts for adv7305a
adv7305a Summary of contents
Page 1
... It includes six high speed video D/A converters with TTL compatible inputs. The ADV7304A/ADV7305A has three separate 10-bit wide input ports that accept data in high definition and/or standard defini- tion video format. For all standards, external horizontal, vertical, ...
Page 2
... ADV7304A/ADV7305A DETAILED FEATURES High Definition Programmable Features (720 p/1080 i) 2 Oversampling (148.5 MHz) Internal Test Pattern Generator (Color Hatch, Black Bar, Flat Field/Frame) Fully Programmable YCrCb to RGB Matrix Gamma Correction Programmable Adaptive Filter Control Programmable Sharpness Filter Control CGMS-A (720 p/1080 i) ...
Page 3
... ADV7304A/ADV7305A–SPECIFICATIONS ( 2.375 V–2.625 2.375 V–3.600 DD_IO Parameter 1 STATIC PERFORMANCE Resolution Integral Nonlinearity 2 Differential Nonlinearity, +ve 2 Differential Nonlinearity, –ve DIGITAL OUTPUTS Output Low Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance ...
Page 4
... ADV7304A/ADV7305A DYNAMIC SPECIFICATIONS Parameter PROGRESSIVE SCAN MODE Luma Bandwidth Chroma Bandwidth SNR SNR SNR HDTV MODE Luma Bandwidth Chroma Bandwidth SNR SNR SNR STANDARD DEFINITION MODE Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermodulation Chroma/Luma Gain Inequality ...
Page 5
... ADV7304A/ADV7305A = 1.235 1520 , REF SET Unit Test Conditions kHz µs µs µs First Clock Generated after This Period µs Relevant for Repeated Start Condition µ MHz Progressive Scan Mode ...
Page 6
... ADV7304A/ADV7305A CLKIN_A P_HSYNC, CONTROL P_VSYNC, I/PS P_BLANK Y9–Y0 C9–C0 CONTROL S_HSYNC, O/PS S_VSYNC CLOCK HIGH TIME, = CLOCK LOW TIME Figure 2. HD 4:2:2 Input Data Format Timing Diagram, Input Mode: PS Input Only, HDTV Input Only (Input Mode at Subaddress 01h = 001 or 010) CLKIN_A P_HSYNC, ...
Page 7
... Y9–Y0 Cb0 Y0 Cr0 CLOCK LOW TIME, = DATA SETUP TIME 10-Bit Interleaved @ 27 MHz, Input Mode: PS Input Only (Input –7– ADV7304A/ADV7305A Gxxx Gxxx Bxxx Bxxx Rxxx Rxxx Crxxx Yxxx DATA HOLD TIME 12 ...
Page 8
... ADV7304A/ADV7305A CLKIN_A P_HSYNC, CONTROL P_VSYNC, I/PS P_BLANK Y9–Y0 CONTROL S_HSYNC, O/PS S_VSYNC CLOCK HIGH TIME, = CLOCK LOW TIME Figure 6. PS 4:2:2 1 Mode at Subaddress 01h = 111) CLKIN_A t 9 S_HSYNC, CONTROL S_VSYNC, I/PS S_BLANK S9–S2 Cb CONTROL S_HSYNC, O/PS S_VSYNC Figure 7. 8-Bit SD Pixel Input Timing Diagram, Input Mode: SD Input Only (Input Mode at Subaddress 01h = 000) ...
Page 9
... Subaddress 01h = 011, 101, or 110) REV Cb0 Cr0 Cb2 Cr2 Cr0 Cb2 Cb4 Cr0 Cb1 t 11 –9– ADV7304A/ADV7305A IN SLAVE MODE Y2 Y3 Cr2 IN MASTER/SLAVE MODE WITH EAV/SAV HD INPUT Y5 Cr4 SD INPUT Y2 ...
Page 10
... ADV7304A/ADV7305A CLKIN_B P_HSYNC, CONTROL P_VSYNC, I/PS P_BLANK Cb0 Y9– CLKIN_A t S_HSYNC, CONTROL S_VSYNC, I/PS S_BLANK S9–S0 Cb0 Figure 10. SD and HD Simultaneous Input, Input Mode: SD and PS 10-Bit (Input Mode at Subaddress 01h = 100) P_HSYNC P_VSYNC P_BLANK Y9– CLKCYCLES FOR 525p CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD Figure 11 ...
Page 11
... Figure 12. HD Input Timing Diagram CLOCK/2 CLOCK/2 Figure 13. SD Timing Input for Timing Mode Figure 14. MPU Port Timing Diagram –11– ADV7304A/ADV7305A Cr0 Cr1 Cr2 Cr3 Cb0 Cb1 Cb2 Cb3 PAL = 132 ...
Page 12
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7304A/ADV7305A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 13
... Pixel Clock Input for HD Only or SD Only Modes This input resets the on-chip timing generator and sets the ADV7304A/ ADV7305A into default register setting. Reset is an active low signal. External Loop Filter for the Internal PLL A 1520 Ω resistor must be connected from this pin to AGND and is used to control the amplitudes of the DAC outputs. Compensation Pin for DACs. Connect 0.1 µ ...
Page 14
... Each slave device is recognized by a unique address. The ADV7304A/ ADV7305A has four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figures 15 and 16. The LSB sets either a read or write operation. Logic Level “ ...
Page 15
... P = STOP BIT REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7304A/ADV7305A except the subaddress registers that are write-only registers. The subaddress register determines which register the next read or write operation accesses. All communica- tions with the part through the bus start with an access to the subaddress register ...
Page 16
... ADV7304A/ADV7305A Subaddress Register 00h Power Mode Register NOTES When enabled, the current consumption is reduced to µA level. All DACs and the internal PLL circuit are disabled This control allows the internal PLL circuit to be powered down and the oversampling to be switched off. ...
Page 17
... –17– ADV7304A/ADV7305A Reset 0 0 Zero must be written 20h to these bits. 0 Disabled 1 Enabled. 0x11h, Bit 2 must also be enabled. 0 Disable Programmable RGB Matrix 1 Enable Programmable RGB Matrix No SYNC SYNC on all RGB Outputs ...
Page 18
... ADV7304A/ADV7305A Subaddress Register 10h HD Mode Register 1 11h HD Mode Register 2 12h HD Mode Register 3 Table IV. HD Mode Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting HD Output Standard HD Input Control Signals HD 625 p HD 720 BLANK Polarity Macrovision for ...
Page 19
... HD Gamma Curve A Gamma Curve Enable Adaptive Filter Mode Adaptive Filter Enable 0 1 10-Bit Interleaved Mode at 54 MHz. –19– ADV7304A/ADV7305A Reset 0 Cb after Falling 4Ch Edge of HSYNC 1 Cr after Falling Edge of HSYNC 0 Reserved 0 8-Bit Input 1 10-Bit Input ...
Page 20
... ADV7304A/ADV7305A Subaddress Register 16h HD Y Color 17h HD Cr Color 18h HD Cb Color 19h Reserved 1Ah Reserved 1Bh Reserved 1Ch Reserved 1Dh Reserved 1Eh Reserved 1Fh Reserved 20h HD Sharpness Filter Gain 21h HD CGMS Data 0 22h HD CGMS Data 1 23h HD CGMS Data 2 24h HD Gamma A ...
Page 21
... HD Adaptive Filter Threshold A Value HD Adaptive Filter Threshold B Value HD Adaptive Filter Threshold C Value –21– ADV7304A/ADV7305A Reset Gain 00hex Gain Gain Gain A = –8 ...
Page 22
... ADV7304A/ADV7305A Subaddress Register 3Eh Reserved 3Fh Reserved 40h SD Mode Register 0 41h Reserved 42h SD Mode Register 1 Table VII. SD Mode Registers Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting SD Standard SD Luma Filter Chroma Filter ...
Page 23
... SD Color Bars 0 1 Reserved Scale SD Y Scale SD Hue Adjust SD Brightness SD Luma SSAF Gain 0 1 Reserved 0 Reserved 0 Reserved 0 –23– ADV7304A/ADV7305A Reset 0 No Pedestal on YUV 00h 1 7.5 IRE Pedestal on YUV 700 mV/300 714 mV/286 700 mV p-p [PAL]; 1000 mV p-p [NTSC 700 mV p-p ...
Page 24
... ADV7304A/ADV7305A Subaddress Register 48h SD Mode Register 5 49h SD Mode Register 6 *For more detail, see Input and Output Configuration section. Table VII. SD Mode Registers (continued) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reserved Reserved SD Double Buffering SD Input Format ...
Page 25
... –25– ADV7304A/ADV7305A Reset 0 Slave Mode 08h 1 Master Mode 0 0 Mode Mode Mode Mode 3 Enabled Disabled No Delay 2 Clock Cycles 4 Clock Cycles 6 Clock Cycles –40 IRE –7.5 IRE ...
Page 26
... ADV7304A/ADV7305A Subaddress Register 59h SD CGMS/WSS 0 5Ah SD CGMS/WSS 1 5Bh SD CGMS/WSS 2 5Ch SD LSB Register 5Dh SD Y Scale Register 5Eh SD V Scale Register 5Fh SD U Scale Register 60h SD Hue Register 61h SD Brightness/WSS 62h SD Luma SSAF 63h SD DNR 0 Table VIII. SD Registers (continued) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting ...
Page 27
... SD Gamma Curve B Data Points SD Gamma Curve B Data Points Field Count Reserved Reserved 0 Reserved 0 Reserved Code X X –27– ADV7304A/ADV7305A Reset 00h Pixels 4 Pixels 8 Pixels 16 Pixels ...
Page 28
... ADV7304A/ADV7305A Subaddress Register 7Ch Reset Register *Line 23 HSYNC VSYNC Subaddress Register 7Dh Reserved 7Eh Reserved 7Fh Reserved 80h Macrovision 81h Macrovision 82h Macrovision 83h Macrovision 84h Macrovision 85h Macrovision 86h Macrovision 87h Macrovision 88h Macrovision 89h Macrovision 8Ah Macrovision 8Bh Macrovision ...
Page 29
... OR DELAY t 27.75ns DELAY Figure 24. Clock Phase with Two Input Clocks –29– ADV7304A/ ADV7305A S_VSYNC S_HSYNC S_BLANK CLKIN_A S9–S0 C9–C0 Y9–Y0 P_VSYNC P_HSYNC P_BLANK CLKIN_B ADV7304A/ ADV7305A S_VSYNC S_HSYNC S_BLANK CLKIN_A S9–S2 C9–C2 Y9–Y2 P_VSYNC P_HSYNC P_BLANK CLKIN_B ...
Page 30
... For correct color decoding, the Pixel Align Bit [Subaddress 01h] must then be set to “l” after a delay of one field. The ADV7304A/ADV7305A is now in Free Run Mode, any changes in the timing information are ignored. CLKIN_A ...
Page 31
... C9–C2 [MSB = C9 4:2:2 YCrCb S9–S0 [MSB = S9 4:2:2 Y Y9–Y0 [MSB = Y9 CrCb C9–C0 [MSB = C9 –31– ADV7304A/ADV7305A 00h, 00h 00h, 10h 00h, 08h 00h, 18h 10h, 40h 10h, 44h 70h, 40h 10h, 44h 10h, 40h 10h, 44h ...
Page 32
... ADV7304A/ADV7305A OUTPUT CONFIGURATION Tables XI–XIII demonstrate what output signals are assigned to the DACs when corresponding control bits are set. RGB/YUV O/P SD DAC O/P 1 Addr 02h, Bit 5 Addr 42h, Bit I/P HD RGB I/P RGB/YUV O/P Format Addr 15h, Bit 1 ...
Page 33
... The Field Count Register at Address 7Bh can be used to identify the number of the active field RTC Mode, the ADV7304A/ADV7305A can be used to lock to an external video source. The Realtime Control Mode allows the ADV7304A/ADV7305A to automatically alter the subcarrier frequency to compensate for line length variations ...
Page 34
... RTC TIME SLOT 01 NOTES 1 i.e., VCR OR CABLE 2 F PLL INCREMENT IS 22 BITS LONG. VALUED LOADED INTO ADV7304A/ADV7305A F SC PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7304A/ADV7305A. 3 PAL LINE NORMAL LINE INVERTED; NTSC CHANGE 4 RESET ADV7304A/ADV7305A DDS ...
Page 35
... VERTICAL BLANKING INTERVAL The ADV7304A/ADV7305A accepts input data that contains VBI data (CGMS, WSS, VITS, and so on and HD Modes. For SMPTE293M (525 p) standards, VBI data can be inserted on Lines each frame, or Lines for ITU-R.BT1358 (625 p) standard. For SD NTSC, this data can be present on Lines 10 to 20; in PAL, on Lines 7 to 22. If VBI is disabled [Address 11h, Bit 4 for HD ...
Page 36
... ADV7304A/ADV7305A HD 4:2:2 to 4:4:4 Interpolation Filters and Chroma SSAF It is recommended to input data in 4:2:2 Input Mode to make use of the HD chroma SSAFs on the ADV7304A/ADV7305A. This filter has pass-band response and prevents signal components from being folded back into the frequency band. In 4:4:4 Input Mode, the video data is already interpolated by the external input device and the chroma SSAFs of the ADV7304A/ ADV7305A are bypassed ...
Page 37
... Figure 39. UV – HDTV 2 –10 –20 –30 –40 –50 –60 –70 – 100 110 Figure 40. UV – –37– ADV7304A/ADV7305A FREQUENCY – MHz Oversampling Filter, Pass Band FREQUENCY – ...
Page 38
... C. The variation of frequency responses can be seen in Figures 41–59. In addition to the chroma filters listed above, the ADV7304A/ ADV7305A contains an SSAF filter specifically designed for and applicable to the color difference component outputs U and V. This filter has a cutoff frequency of approximately 2.7 MHz and – 3.8 MHz, as shown in Figure 41. This filter can be controlled via Address 42h, Bit 0 ...
Page 39
... Figure 47. Luma SSAF Filter MHz –2 –4 –6 –8 –10 – Figure 48. Luma SSAF Filter, Programmable Responses 100 110 Figure 49. Luma SSAF Filter, Programmable Gain –39– ADV7304A/ADV7305A FREQUENCY – MHz FREQUENCY – MHz ...
Page 40
... ADV7304A/ADV7305A 1 0 –1 –2 –3 –4 – FREQUENCY – MHz Figure 50. Luma SSAF Filter, Programmable Attenuation 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 51. Luma CIF LP Filter 0 –10 –20 –30 –40 –50 –60 –70 ...
Page 41
... REV –10 –20 –30 –40 –50 –60 – –10 –20 –30 –40 –50 –60 – –41– ADV7304A/ADV7305A FREQUENCY – MHz Figure 58. Chroma CIF LP Filter FREQUENCY – MHz Figure 59. Chroma QCIF LP Filter ...
Page 42
... Address 08h: 92h Address 09h: 7Ch ) ( ) + × 0722 . B ' When the programmable RGB matrix is not functional, the ADV7304A/ADV7305A automatically scales YCrCb inputs to ) − all standards supported. For SMPTE293M, the register values are as follows: ) − Address 03h: 03h Address 04h: 1Eh ...
Page 43
... The ADV7304A/ADV7305A provides a range of ±22.5° in increments of 0.17578125°. For normal operation (zero adjust- ment), this register is set to 80h. FFh and 00h represent the attainable upper and lower limit (respectively) of adjustment ...
Page 44
... ADV7304A/ADV7305A Gamma Correction [Subaddresses 21h–37h for HD; Subaddresses 66h–79h for SD] Gamma correction is available for SD and HD video. For each standard there are 20 8-bit wide registers. They are used to program the Gamma Correction Curves A and B. HD Gamma Curve A is programmed at Addresses 24h–2Dh and HD Gamma Curve B at 2Eh– ...
Page 45
... FILTER CONTROL [Subaddresses 20h and 38h–3Dh] There are three filter modes available on the ADV7304A/ ADV7305A: Sharpness Filter Mode and two adaptive filter modes. HD Sharpness Filter Mode To enhance or attenuate the Y signal in the frequency ranges shown in Figure 63, the following register settings must be used: HD Sharpness Filter must be enabled and HD Adaptive Filter Enable must be set to disabled ...
Page 46
... ADV7304A/ADV7305A Figure 64. HD Sharpness Filter Control with Different Gain Settings for HD Sharpness Filter Gain Value HD Sharpness Filter and Adaptive Filter Application Examples HD Sharpness Filter Application The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The register settings in Tables XIX and XX are used to achieve the results shown in Figure 64 ...
Page 47
... SHARPNESS MODE NOISE SIGNAL PATH INPUT FILTER BLOCK Y DATA INPUT MAIN SIGNAL PATH Figure 68. DNR Block Diagram –47– ADV7304A/ADV7305A 16 pixels DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN CORING GAIN DATA CORING GAIN BORDER FILTER SUBTRACT SIGNAL OUTPUT IN THRESHOLD < ...
Page 48
... ADV7304A/ADV7305A The Digital Noise Reduction Registers are three 8-bit wide registers. They are used to control the DNR processing. Coring Gain Border [Address 63h, Bits 3–0] These four bits are assigned to the gain factor applied to the border areas. In DNR Mode, the range of gain values is 0–1, in increments of 0 ...
Page 49
... AD8061. More information on line driver buffering circuits is given in the relevant op amp data sheets. An optional analog reconstruction LPF might be required as an antialias filter if the ADV7304A/ADV7305A is connected to a device that requires this filtering. The filter specifications vary with the application, see Table XXIII. ...
Page 50
... PCB Board Layout Considerations The ADV7304A/ADV7305A is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7304A/ ADV7305A imperative that great care be given to the PC board layout. The layout should be optimized for the lowest BNC O/P 75R noise on the ADV7304A/ADV7305A power and ground lines ...
Page 51
... For optimum per- formance, the analog outputs should each be source and load terminated, as shown in Figure 79. The termination resistors should be as close as possible to the ADV7304A/ADV7305A to minimize reflections. Any unused inputs should be tied to ground. POWER SUPPLY DECOUPLING FOR ...
Page 52
... C19–C14, that comprise the 6-bit CRC check sequence are calculated automatically on the ADV7304A/ ADV7305A based on the lower 14 bits (C0–C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the ...
Page 53
... WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7304A/ ADV7305A is configured in PAL Mode. The WSS data is 14 bits long. The function of each of these bits is shown in Table XXVI. The WSS data is preceded by a run-in sequence and a start code (see Figure 82 WSS [Address 59h, Bit 7] is set to a Logic “ ...
Page 54
... Lines 21 and 284 are generated automatically by the ADV7304A/ 50 IRE 40 IRE REFERENCE COLOR BURST FREQUENCY = F ADV7305A. All pixels inputs are ignored during Lines 21 and 284 if closed captioning is enabled. FCC Code of Federal Regulations (CFR) 47, Section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284. ...
Page 55
... Appendix D TEST PATTERNS The ADV7304A/ADV7305A can generate SD and HD test patterns. Figure 84. NTSC Color Bars Figure 85. NTSC Black Bar (–21 mV, 0 mV, +3.5 mV, +7 mV, +10.5 mV, +14 mV, +18 mV, +23 mV) Figure 86. 525 p Hatch Pattern REV. A ADV7304A/ADV7305A Figure 87. PAL Color Bars Figure 88. PAL Black Bar (–21 mV, 0 mV, +3.5 mV, +7 mV, +10 ...
Page 56
... ADV7304A/ADV7305A Figure 90. 525 p Field Pattern Figure 91. 525 p Black Bar (–35 mV, 0 mV, +7 mV, +14 mV, +21 mV, +28 mV, +35 mV) Figure 92. 625 p Field Pattern Figure 93. 625 p Black Bar (–35 mV, 0 mV, +7 mV, +14 mV, +21 mV, +28 mV, +35 mV) –56– REV. A ...
Page 57
... Table XXXI. PAL Black Bar Pattern Output on DAC A Subaddress Register Setting 40h 11h 4Ch CBh 4Dh 8Ah 4Eh 09h 4Fh 2Ah REV. A ADV7304A/ADV7305A Table XXXII. 525 p Hatch Pattern on DAC D Subaddress Register Setting 00h 12h 01h 10h 02h 20h 10h 40h 11h 05h ...
Page 58
... ADV7304A/ADV7305A Appendix E SD TIMING MODES [Subaddress 4Ah] Mode 0 (CCIR-656): Slave Option (Timing Register 0 TR0 = The ADV7304A/ADV7305A is controlled by the start active video (SAV) and end active video (EAV) time codes in the pixel data. All ANALOG VIDEO INPUT PIXELS Y ...
Page 59
... REV. A VERTICAL BLANK ODD FIELD VERTICAL BLANK 318 313 314 315 316 317 EVEN FIELD Figure 96. SD Master Mode 0, PAL Figure 97. SD Master Mode 0 Data Transitions –59– ADV7304A/ADV7305A DISPLAY DISPLAY 334 335 336 319 320 ...
Page 60
... HSYNC BLANK ODD FIELD FIELD retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7304A/ADV7305A automatically blanks all normally blank lines as per CCIR-624. HSYNC is input on the S_HSYNC pin, BLANK on the S_BLANK pin, and FIELD on the S_VSYNC pin. VERTICAL BLANK ...
Page 61
... Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode, the ADV7304A/ADV7305A can generate hori- zontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., HSYNC FIELD PAL = 12 NTSC = 16 BLANK ...
Page 62
... ODD FIELD A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7304A/ADV7305A auto- matically blanks all normally blank lines as per CCIR-624. HSYNC is input on the S_HSYNC pin, BLANK on the S_BLANK pin, and FIELD on the S_VSYNC pin ...
Page 63
... Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = this mode, the ADV7304A/ADV7305A can generate hori- zontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd HSYNC VSYNC PAL = 12 ...
Page 64
... Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode, the ADV7304A/ADV7305A accepts or generates horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, DISPLAY ...
Page 65
... INPUT CODE 1023 OUTPUT VOLTAGE +350mV VIDEO ACTIVE 0mV 64 –300mV –350mV Figure 110. Output Levels for Full Input Selection –65– ADV7304A/ADV7305A EIA-770.3, STANDARD FOR Y OUTPUT VOLTAGE +700mV VIDEO ACTIVE +300mV 0mV –300mV EIA-770.3, STANDARD FOR Pr/Pb OUTPUT VOLTAGE +350mV +300mV ...
Page 66
... ADV7304A/ADV7305A Appendix G VIDEO STANDARDS SMPTE274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 2116 2156 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 SAV/EAV: LINE 563–1125 SAV/EAV: LINE1–20; 561–583; 1124–1125 SAV/EAV: LINE 21– ...
Page 67
... Figure 115. SMPTE296M (720 p) VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 116. SMPTE274M (1080 i) –67– ADV7304A/ADV7305A ACTIVE VIDEO ACTIVE VIDEO DISPLAY ...
Page 68
... ADV7304A/ADV7305A 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90 CCW Revision History Location 11/02—Data Sheet changed from REV REV. A. Changes to Figure Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Added Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Changes to Table XII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Changes to Table XIII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Changes to the Realtime Control, Subcarrier Reset, Timing Reset section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Changes to SD SUBCARRIER FREQUENCY REGISTERS [Subaddress 4Ch– ...